Simulation Results: rom_ctrl/32kb

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 94.00 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
93.22%
V3
65.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 139.469us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 175.149us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 1075.053us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 560.986us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 497.797us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 169.476us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 1075.053us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 497.797us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 385.522us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 213.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 170.276us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 16.000s 2209.397us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.000s 2808.104us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.000s 169.020us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 2372.451us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 2372.451us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 175.149us 1 1 100.00
rom_ctrl_csr_rw 4.000s 1075.053us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 497.797us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 128.882us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 175.149us 1 1 100.00
rom_ctrl_csr_rw 4.000s 1075.053us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 497.797us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 128.882us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 604.516us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
rom_ctrl_tl_intg_err 35.000s 3878.411us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 139.469us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 139.469us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 139.469us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 35.000s 3878.411us 25 25 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
rom_ctrl_kmac_err_chk 7.000s 2808.104us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 64.000s 2685.534us 16 20 80.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.000s 604.516us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 129.000s 4274.252us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 13 20 65.00
rom_ctrl_stress_all_with_rand_reset 98.000s 6691.789us 13 20 65.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 7 test runs
rom_ctrl_stress_all_with_rand_reset 2332402472707169417858817102358965649349392175750706041324354577576464457770 89
UVM_INFO @ 758152495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 54099996267593081796026239301517923254469030240726740969288905981440365012365 90
UVM_INFO @ 300696369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 30097897803484157262496223407327759747647457292494861530797696216224264512264 90
UVM_INFO @ 416628921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 24079552273175268947344664984206825376985947567374717402292769093931751815751 93
UVM_INFO @ 696861861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 2932726730263223764471392568179207877848992964013574093203676878093722899617 91
UVM_INFO @ 199698107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 29418814886402952289892956795916360707109716181398760534189908698336503988179 91
UVM_INFO @ 1008832524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 105502865100470820473439108669654600364528378846712595042162928569811359408707 91
UVM_INFO @ 310504622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 88734352913088159755542030133541418905106347835531162063578328207282202125795 87
UVM_INFO @ 361177561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 84584524597762631173702662926824092976714463828840031405896564090694218044933 99
UVM_INFO @ 3890507071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 113269557468114015103204256644714474639815672978757410310659750856326575947993 92
UVM_INFO @ 4451224353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 27013470205600717316913184820701603267419303183687770114975191832178968353955 97
UVM_INFO @ 4376284437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 101164284659012372436907590866293914556972967425857636444646553681354184202181 88
UVM_INFO @ 170276305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 6268236371978282305827504559598772248901623589963100408727334116231259903263 88
UVM_INFO @ 348615893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---