Simulation Results: rom_ctrl/64kb

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 94.02 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.74 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.000s 673.962us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.000s 292.546us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 8.000s 293.303us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 287.854us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 1073.270us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.000s 754.494us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 8.000s 293.303us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1073.270us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 1116.319us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 1305.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 8.000s 983.753us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 32.000s 4019.650us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 13.000s 697.028us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.000s 544.850us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 4979.350us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.000s 4979.350us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.000s 292.546us 1 1 100.00
rom_ctrl_csr_rw 8.000s 293.303us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1073.270us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 552.964us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.000s 292.546us 1 1 100.00
rom_ctrl_csr_rw 8.000s 293.303us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1073.270us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.000s 552.964us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.000s 4332.401us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
rom_ctrl_tl_intg_err 73.000s 384.418us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.000s 673.962us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.000s 673.962us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.000s 673.962us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 73.000s 384.418us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
rom_ctrl_kmac_err_chk 13.000s 697.028us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 139.000s 9950.957us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 35.000s 4332.401us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 254.000s 2592.478us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 104.000s 18813.162us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 41422805917303345204358092039888431373558868291886315124497703029738822647548 88
UVM_INFO @ 983753180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 76098180059749053492202004919180087167647578350837217134226995307731183032328 88
UVM_INFO @ 991684602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---