Simulation Results: rstmgr

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.92 %
  • code
  • 99.56 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 99.90 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.890s 75.432us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.550s 64.508us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.890s 122.699us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.690s 44.939us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.800s 84.424us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00
rstmgr_csr_aliasing 1.690s 44.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.070s 147.584us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.510s 46.855us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.630s 89.232us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 6.570s 632.134us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 6.570s 632.134us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 6.570s 632.134us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 6.570s 632.134us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 27.410s 3234.715us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 2.380s 223.145us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.090s 75.410us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.090s 75.410us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.550s 64.508us 1 1 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00
rstmgr_csr_aliasing 1.690s 44.939us 1 1 100.00
rstmgr_same_csr_outstanding 1.750s 66.869us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.550s 64.508us 1 1 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00
rstmgr_csr_aliasing 1.690s 44.939us 1 1 100.00
rstmgr_same_csr_outstanding 1.750s 66.869us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 37.290s 6789.573us 5 5 100.00
rstmgr_tl_intg_err 7.090s 615.670us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 37.290s 6789.573us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 37.290s 6789.573us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 7.090s 615.670us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.520s 70.012us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 6.700s 486.747us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.380s 297.978us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 37.290s 6789.573us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.320s 36.814us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 38865489941926477750770547144567236342025348638072088876508114782301254019094 121
UVM_INFO @ 231219998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---