Simulation Results

Simulation Results: rv_dm/use_dmi_interface

17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.33 %

code
83.41 %

assert
96.90 %

func
96.67 %

block
93.85 %

line
94.33 %

branch
83.33 %

toggle
75.62 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		44.44%
V2S		96.00%
V3		25.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	49.000s	858.088us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	48.000s	604.251us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	51.000s	860.177us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	50.000s	7669.544us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	49.000s	1172.535us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	70.000s	15573.591us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	53.000s	14930.633us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	75.000s	65561.882us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	202.000s	130924.537us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	403.280us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	51.000s	574.331us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	51.000s	749.908us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	52.000s	225.822us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	38.000s	129.276us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	48.000s	416.171us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	42.000s	320.961us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	49.000s	586.645us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	403.280us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	39.000s	194.429us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	45.000s	837.748us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	51.000s	749.908us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	49.000s	195.228us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	44.000s	583.410us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	45.000s	201.508us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	85.000s	36313.173us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	67.000s	4694.139us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	41.000s	61.996us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	67.000s	4694.139us	1	1	100.00
	rv_dm_csr_rw	45.000s	201.508us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	37.152us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	35.000s	108.871us	1	1	100.00

80/180 passed

44.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	49.000s	858.088us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	50.000s	159.091us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	39.000s	172.443us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	44.000s	274.924us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	41.000s	655.787us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	54.000s	8850.785us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	52.000s	4332.651us	0	20	0.00
bad_sba				3	20	15.00
	rv_dm_bad_sba_tl_access	50.000s	125.890us	3	20	15.00
sba_autoincrement				3	20	15.00
	rv_dm_autoincr_sba_tl_access	277.000s	159717.647us	3	20	15.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	34.000s	156.967us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	41.000s	563.991us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	48.000s	179.075us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	50.000s	227.202us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	41.000s	10448.745us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	98.000s	8555.565us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	31.000s	59.653us	1	1	100.00
stress_all				1	20	5.00
	rv_dm_stress_all	10800.000s	0.000us	1	20	5.00
alert_test				10	10	100.00
	rv_dm_alert_test	49.000s	125.529us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	49.000s	488.462us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	49.000s	488.462us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	67.000s	4694.139us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	583.410us	1	1	100.00
	rv_dm_csr_rw	45.000s	201.508us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	2140.704us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	67.000s	4694.139us	1	1	100.00
	rv_dm_csr_hw_reset	44.000s	583.410us	1	1	100.00
	rv_dm_csr_rw	45.000s	201.508us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	2140.704us	5	5	100.00

V2S

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	52.000s	1434.150us	5	5	100.00
	rv_dm_tl_intg_err	56.000s	4579.267us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	56.000s	4579.267us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	41.000s	563.991us	2	2	100.00
	rv_dm_debug_disabled	41.000s	33.510us	1	2	50.00
sec_cm_lc_dft_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	41.000s	563.991us	2	2	100.00
	rv_dm_debug_disabled	41.000s	33.510us	1	2	50.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	49.000s	858.088us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				9	10	90.00
	rv_dm_buffered_enable	45.000s	291.343us	9	10	90.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	142.400us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	43.000s	142.400us	4	4	100.00
sec_cm_exec_ctrl_mubi				9	10	90.00
	rv_dm_buffered_enable	45.000s	291.343us	9	10	90.00

5/20 passed

25.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				5	20	25.00
	rv_dm_stress_all_with_rand_reset	76.000s	4700.563us	5	20	25.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	116.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				38 test runs
	rv_dm_sba_tl_access	81743203094945332881767849055077301660621370014112919362270431401038714798696	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_autoincr_sba_tl_access	68112028449744973607651171289165689051250322603174703826721767181829876688017	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23866
	rv_dm_sba_tl_access	19761775658285087566757832189731434540187575447373238242383913373947112636537	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_autoincr_sba_tl_access	13680985336884417167168184682018247046684686334546292348843543864700276011279	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	69073670730783257203599418972563549121017194270569220822068582801394784636812	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23857
	rv_dm_autoincr_sba_tl_access	98003692512564437137796519841209956202074969284337660480413806839974608081199	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23734
	rv_dm_sba_tl_access	41626400754174721450309502466060794973573338478738930757028429616204747647197	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_autoincr_sba_tl_access	54865153271756654772087709079483826957002126666392044467457840472607579704667	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	53047897857505918646217811117244030007146210856548844512298227764048071752827	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_delayed_resp_sba_tl_access	18311670303364374864948859935053086211576528603283189569928516310593918122494	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23782
	rv_dm_sba_tl_access	114348264700988570418719054281499565640512145994350459723406631196439273279003	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_sba_tl_access	40436651027193585266979595696649051046678564893318456672793117312713072899532	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23803
	rv_dm_bad_sba_tl_access	60054879809961232350832303702868432633582537359580924272217575089097879525931	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23904
	rv_dm_sba_tl_access	58106750981943319269698737356984536684546063505868907135578514991899417880606	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_bad_sba_tl_access	23282319198434737833579543404835376456312958817443298952955284748819557392763	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23761
	rv_dm_autoincr_sba_tl_access	23995621991004758192780369665479831744013844041276008757692274059803389146176	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23926
	rv_dm_sba_tl_access	103965810454665939292671755724473041210395078197440853856350182610913273696690	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_autoincr_sba_tl_access	46535482008863506115184928415090854749712200591949016943775549364671288320201	156	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24031
	rv_dm_sba_tl_access	675975454527945586161517987390957593241314555832126679574751785102265407480	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23828
	rv_dm_sba_tl_access	79566578642624685958266314583627675597331953021225835075503357724106660794847	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	51747020738679531065158091277489455927600711877343176204372708791465098258436	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_sba_tl_access	2066204483064443455824476764079718963285057296670267972852389372292775438458	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_sba_tl_access	89719080763602377517761885194620436227344666140649570460124834502016853441079	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23833
	rv_dm_bad_sba_tl_access	83133995522332263984150759937054511937414093272112719284423080104134248157024	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23827
	rv_dm_sba_tl_access	111089217996194712905066221456318782075572968464522546800473079883052935693878	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_autoincr_sba_tl_access	7180079638987423946690625540012285906753406169430384830820185959404930737131	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23880
	rv_dm_sba_tl_access	78181739059950232700488454518966413291496222073260140839062921418102212974575	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_bad_sba_tl_access	34988325894378202891372417758304387298126294231929473870209036180331391863285	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23925
	rv_dm_sba_tl_access	62738407278576998026354799381175032316492245602568618792260277237269143825813	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23858
	rv_dm_autoincr_sba_tl_access	35747047009937490400533361604725872561542330916209549061332664298323612388701	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_sba_tl_access	34626409241419307901428614562586149986299206135324825495099983125774331999965	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23823
	rv_dm_bad_sba_tl_access	53798091935730545097304080538089402836425317647602051237705575159528876153308	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10108
	rv_dm_autoincr_sba_tl_access	16175833708174171075000061251001232431722828321186928470175128108442167217079	150	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24086
	rv_dm_sba_tl_access	42101917739172494202215589472829161189927689398490291869224501931876321699116	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23818
	rv_dm_sba_tl_access	51258671280657636249934874675510922840637950042851246075200784552391153457761	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23835
	rv_dm_sba_tl_access	25039006571640110386809779410099742415945560978472486914292648772421070497164	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23776
	rv_dm_bad_sba_tl_access	26277451597538592615839373308632237195220132810691346821644105749205205774900	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23957
	rv_dm_autoincr_sba_tl_access	96925601090329722439395650916069774949888739214636492646692724097175756296020	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23785
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				36 test runs
	rv_dm_delayed_resp_sba_tl_access	51540131428605133646787797787474537689641460144074397428652109537039412399576	107	UVM_INFO @ 117149671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	92531001864652745496460430765352509425027011955200634488284718589975649663034	107	UVM_INFO @ 393242605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35539489919111465801205027098235171162299564188226298396577084830028284676826	107	UVM_INFO @ 72819148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	12465401699714012463449890985643806379686153231241222837275727931178056474988	107	UVM_INFO @ 57299428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	28682071440375793995422311661002120717584092908913354402542838104933883825410	107	UVM_INFO @ 444296696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	44300953564485160915485060339762995359435583957018566636615276513064831281973	107	UVM_INFO @ 371269254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	72390300109047140875637305991953201509546910308654334937631034980322209914687	107	UVM_INFO @ 59420122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	51912002786124837200239528784796185209403806934599067668631469852921199451317	107	UVM_INFO @ 159978760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	15128069072441428076614952801702139023067609972665169538068338501168950031733	107	UVM_INFO @ 1657576592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	95856771702567395816969895660279382302518536020080590548473816208831159190954	107	UVM_INFO @ 181204026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	84784228882403005290977329312028909110941598789284020189707194711175354748253	107	UVM_INFO @ 370985539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	75387443252315568450012489930622272371598423382011703661959666641093961727291	107	UVM_INFO @ 546931393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	16689153922661895542783322262643536549008149903629227380521548457948389221450	107	UVM_INFO @ 154147446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	106192833773727665451038071306238978942419536131942729716437169672793479873689	107	UVM_INFO @ 334144218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	95461254866413585297492817843941157307922693964124868431835449601269927883779	107	UVM_INFO @ 61229721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	53139261052146007713247369917118445351824454660838685909212928485530540826685	107	UVM_INFO @ 505083174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	93095001734435498238019010150740356071816686559747589072078761226236927338791	107	UVM_INFO @ 1425356052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	53551499272322645735216233734447416393096047657081797057353783136197202004919	107	UVM_INFO @ 83305278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	113918113023351248186225736246446219632300054470579013867812654390690450511191	107	UVM_INFO @ 200014659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	84051015239877771957481122634254556430397083864481526768911962692105549694238	107	UVM_INFO @ 103096807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	56883902123811567949130531241167254751779100754033438307332833919873092371445	107	UVM_INFO @ 125012931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72080965043026896696100742555523621796332044802536215518327105446579093158985	107	UVM_INFO @ 210282646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	17419889803945343991630120227856425028145342885785127703376088638510932435525	107	UVM_INFO @ 229908123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	99484249152243335071539613262179562603969470116752395610934481922093627091466	107	UVM_INFO @ 194401289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	68242231199069031348106640344361686396860590495365069477696133303226106341387	107	UVM_INFO @ 610348231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2674957955250576431019123720203995118059688880720530276286437281003709592619	107	UVM_INFO @ 127274122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	70010322551032633372216771386320966005137794536694416752000398064591719062493	122	UVM_INFO @ 3259577662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	96336878142213885808245661753604303844745919195289582963658923331051708975809	107	UVM_INFO @ 54683025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	81968940185820523376899537881479146305320900501421931759989064262258024430815	107	UVM_INFO @ 176558218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	63068687784517988883996436528470823292621502744387828183327233451870136967330	107	UVM_INFO @ 125890296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	37188542877286270330148747573900047605807268507270686507472933332960259166099	107	UVM_INFO @ 301261448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10404796950952322213730822629245911342071675811087046731865734542453149402692	107	UVM_INFO @ 545616322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	70967730344556192196710783534043285841642832252353478412889812866082216860273	107	UVM_INFO @ 248653426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35724768335730440385255442980345694237223670896171965364603930443281186555841	107	UVM_INFO @ 516317563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	110453887701410764266404659756089332056049169938754285201794772858979626909438	107	UVM_INFO @ 7864225369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	75141756382953593065441626863548116187935815168129842664901986724283611406214	107	UVM_INFO @ 270756115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				15 test runs
	rv_dm_hart_unavail	7291997171460686244785566351063429257295622332436874297967032057064977484090	87	UVM_INFO @ 65431895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	6510594980369466802194044116811750413843093434039813525502308651258629737869	87	UVM_INFO @ 155584426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	31167571105863807505851887895447873044323224318645073017689069308905146946287	87	UVM_INFO @ 227202359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	590758582293817199018689650763192669848695742786037045923269526204981851818	98	UVM_INFO @ 229720907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	3715227759015289786300750976370043802102384711198038789987988838813581502294	87	UVM_INFO @ 385536617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	87269008701424435676337023785782516976270487400094284246486596136743015006325	87	UVM_INFO @ 74696383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	90023786790084981450433885188821664347380282842758790253035442067161144204609	90	UVM_INFO @ 537294152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	935578329804223638388844202558875571771818932573691202632926642863760053565	99	UVM_INFO @ 355423174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	21372625153757075399752349174399547614168224534998987733279032864115715819750	93	UVM_INFO @ 3309982879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	99390722800750369113163339523195308242748766059565029132972484316497703222123	94	UVM_INFO @ 3685766972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35380707567993986454863348764302044558202779614802135002722895172122391042962	91	UVM_INFO @ 2149461920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	48286570847938545923405633995051558015315214899688410296914545855353710821005	91	UVM_INFO @ 2157865856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	18345217961589017768956053275170300473870576978803964671598174610298928019458	89	UVM_INFO @ 654782100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	19876797826075303927126117623716372816588113769592606061573253507693261381414	90	UVM_INFO @ 2072133467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	98098994692991740278189593404178940576472069923023239970833798902722074770686	97	UVM_INFO @ 370077657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				11 test runs
	rv_dm_jtag_dmi_debug_disabled	25350365786314031087214895959129163452655794614704273460298856338037274845125	87	UVM_INFO @ 156966636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	70340112966418078221738323542497911841146039943988541319583406588406797864487	90	UVM_INFO @ 785750531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	110965094369644463946534818649807014013315374287369520977570258111740744809222	91	UVM_INFO @ 234281791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	110874965063885561824830939406646001329821039998726537894064689917734924670764	87	UVM_INFO @ 124355374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98429405149616620509479872363646746888479097229129645752417904514455235665143	88	UVM_INFO @ 389978896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	98256993672099370919530529166394061519096135442520251280870708127722233521202	92	UVM_INFO @ 294124289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	94714590762149482531055920235705053945543266560464964144383461864949965119933	88	UVM_INFO @ 168510814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	91097186417146474687284090327879943201222103728742756321494725122015277554764	136	UVM_INFO @ 1716381395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	74225132190011485064202296014684915371250816793810697636955421011661385942200	101	UVM_INFO @ 4071993276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	8377415963667599369345176413768846899196877498565902860942797937871155594730	101	UVM_INFO @ 3754116472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	42481118521325318873266189766039177720799962184034097654921412303950279000385	90	UVM_INFO @ 401141878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				7 test runs
	rv_dm_mem_tl_access_resuming	74052415451119605708449737241952579562662776723265872612770395441149923209385	87	UVM_INFO @ 225821983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	84037516224702738178217955023971626001853156422653113604374299428616414629308	87	UVM_INFO @ 178436438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	52766316695265308382830874085658558686268938642493593927964091231443528125552	132	UVM_INFO @ 7489515099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96364015985692381886399881237049783554166575646605965631584878424406755435000	114	UVM_INFO @ 2925711726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	70774537554169689124112985555571239668642375404310431139233231316453420677716	91	UVM_INFO @ 140771035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	114122071260506478040185116482636831131097834245832200818819138001351327246623	113	UVM_INFO @ 4826953403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	7169157875634284359335015831937955280669946136159854406737493149856831501792	89	UVM_INFO @ 339457215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	rv_dm_scanmode	13322695042106532084151134424021094592899739761913686169725399768940131455480	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	109031332233188272666856977336642837581336956963109340109577220342855904538528	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	80808993181364588273712016759685480636457905308200393818360030847759881614079	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	14721772630504667639367658971961154659301343778704017585463484910898520369052	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	103986451261786627713145799928831905423751232205824883772962216028653501313432	91	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				5 test runs
	rv_dm_stress_all_with_rand_reset	71209975856132356090576628447093538281516127766315733418048692913459111899391	104	UVM_INFO @ 4071456265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	69878381549811468550455626604489145677502170734095273112386419683680238442513	102	UVM_INFO @ 1174146814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104143701871420221278779031611136618769633400858090244585850938425672925770389	96	UVM_INFO @ 2895065054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5904034252246348450734945664432372465304594357556186440941773074666611776288	107	UVM_INFO @ 1569175032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	96178024019903974947167552120925649682560738316821510729308573186266219957737	139	UVM_INFO @ 3690125821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed				1 test run
	rv_dm_debug_disabled	16348297501763161283947462740147840131910353866349058033503722994113465687436	90	UVM_ERROR @ 33509557 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) UVM_INFO @ 33509557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	15311605166836123924701805860187402971031171317947086658781750412642121999141	92	UVM_INFO @ 331508116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	rv_dm_stress_all	83369299723380306673123106709540363504739620602410702714965691437797708301184	None