Simulation Results: rv_timer

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.18 %
  • code
  • 90.45 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
37.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 123.972us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 16.751us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 16.176us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 329.637us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 26.313us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 26.954us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 16.176us 5 5 100.00
rv_timer_csr_aliasing 2.000s 26.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 9.000s 13744.970us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1547.223us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 706.000s 1727688.882us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 706.000s 1727688.882us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 7.000s 3928.513us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 12.688us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 29.636us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 4.000s 204.525us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 4.000s 204.525us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 16.751us 1 1 100.00
rv_timer_csr_rw 1.000s 16.176us 5 5 100.00
rv_timer_csr_aliasing 2.000s 26.313us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 105.626us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 16.751us 1 1 100.00
rv_timer_csr_rw 1.000s 16.176us 5 5 100.00
rv_timer_csr_aliasing 2.000s 26.313us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 105.626us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 1058.622us 5 5 100.00
rv_timer_tl_intg_err 2.000s 275.445us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 275.445us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 10 0.00
rv_timer_min 2.000s 667.267us 0 10 0.00
max_value 1 10 10.00
rv_timer_max 2.000s 265.992us 1 10 10.00
stress_all_with_rand_reset 14 20 70.00
rv_timer_stress_all_with_rand_reset 56.000s 55234.209us 14 20 70.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 28 test runs
rv_timer_min 48457094076822595961738140779197469201633119994130206194859672805957511910517 84
UVM_INFO @ 83694988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 113604140135817311488007698290589092814329983878308105955396019794136216160336 84
UVM_INFO @ 2174264048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 59083520151483404709694598309431249757953427098912887578866343541569997457731 84
UVM_INFO @ 667266744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67631544114392045231115058529732463739009829209494097331819840159960895766272 84
UVM_INFO @ 14673911250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 105072616446765709380971904479459433278664131517174841278069911085455933099952 85
UVM_INFO @ 93911503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 70780064853128202720215989708383022362288691688090383265142514133301703473592 84
UVM_INFO @ 574057330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 4797141198715906167183569205253401982571185303175111107354190646407044320093 86
UVM_INFO @ 215583623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2943737820121776650381416619848296880093859079995880952824562093615420426318 84
UVM_INFO @ 340791542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 58935078735442989311247201553012037356044784483624999011342815038669774839171 84
UVM_INFO @ 689323972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 72705773131224280712772509211701681500103839808734826208002440005041646351788 84
UVM_INFO @ 774754041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 10860789435616728491545393953588002852692382048026861073587196307978476634430 84
UVM_INFO @ 112728873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 44060204224210646081797598740181744623102423515055494354786087977786722358651 84
UVM_INFO @ 332564118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 74779214215499740462561025446870142489045132307211086079060219628268476078819 84
UVM_INFO @ 13744970072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 36308995539464483333806417297890475624407360485435484681989682365410450635537 84
UVM_INFO @ 68079542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 76846013853717659221706512820034312216132105428139961790053254872699352322533 84
UVM_INFO @ 169059959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 37637230680140351288375072472861410982027209424855207247983103079558346607235 85
UVM_INFO @ 126960785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 15434797436174538372324502293766742159081146408116078972360859749384605088510 87
UVM_INFO @ 958112313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 31703417640023080199896272451189742528372905930296184224652229367863600828996 84
UVM_INFO @ 231552895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 112899303405978442234255092103198850391676127896741766231767785378346135229824 84
UVM_INFO @ 5498338490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 99458877710427525442549162242435071140549808183218282608525224471097477145348 84
UVM_INFO @ 56829970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 10445667708305814272193786015461778477059616875162359846953893404428051505607 84
UVM_INFO @ 1145569830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50686190283273072661958958200404756713689772099792454710031941001799901246047 86
UVM_INFO @ 340318539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 90606509395472068559152017206238561694716614087653614353326536421372171868821 84
UVM_INFO @ 1339998669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 55527935930831673695793261071902402324431726701703781735596090931395840355298 84
UVM_INFO @ 233879757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 75084237835330719109486006947527043878382989038930042381492689205443201754031 84
UVM_INFO @ 145590306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 44163826526596991514341029219159812154646118277564921125060249642658030571199 84
UVM_INFO @ 545874211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 99981478218957134974668102863752656283216022045173976511983608167101950380350 85
UVM_INFO @ 736612789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 39431744424975287345984294866351152222682029270329629607432932811912435481807 84
UVM_INFO @ 936735021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 80403970271639935984622522899054597538438726024666452542970826366126106539269 84
UVM_INFO @ 340085207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 62042622596906203682666912683709591960671903725278006756922093342282185737672 84
UVM_INFO @ 265991671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 109999588004434345512830343409178657406127404701997744990788916770613431503322 84
UVM_INFO @ 45555156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 50394386540182930002909411056442041465171248831587556709885800428719376670973 84
UVM_INFO @ 182098309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 52504586868558022203616698846000193909609109127201195380192027879818695804588 84
UVM_INFO @ 350330255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 56631682219825062396575503218682212818653246237255787322654716249620867898943 84
UVM_INFO @ 44491433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 43991662811988614124978283689199092189687323831733281401444262450552914212763 84
UVM_INFO @ 183373925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 88036239583695416966126504114009414202346416267379419171043616311813438363835 84
UVM_INFO @ 176483373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 103395692730422011147783571461916813885517173278972002064809292082052655018735 84
UVM_INFO @ 475449312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 4 test runs
rv_timer_stress_all_with_rand_reset 15662428956141638855145762248966915262378502350474106864456366019276776789993 145
UVM_INFO @ 61020423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 11428385155592075392632223925638365335370967290574007325002012636502771299046 197
UVM_INFO @ 3534601587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 73618277938290909232433699810520818512434563572157264097519416163899072082668 394
UVM_INFO @ 16057721857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 19895753464484712501877393653611351109060487201072166556023384410374854186992 262
UVM_INFO @ 6241412695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 84771311255698136791008657448067240227691762356118112130303208976739628109924 256
UVM_INFO @ 8387320654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 68159456090146573318657037945317484184417090534055897854274474229113653781826 108
UVM_INFO @ 5249719218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---