Simulation Results: sram_ctrl/main

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.92 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 96.80 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 6.000s 697.905us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 17.684us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 133.155us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 99.269us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 65.665us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 355.069us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 133.155us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 65.665us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 311.000s 52574.196us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 158.000s 24802.197us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 51.000s 12389.515us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 244.000s 20162.032us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 223.000s 15157.919us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 65.000s 38670.346us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 54.000s 14154.003us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 33.000s 18290.952us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 668.489us 8 8 100.00
sram_ctrl_partial_access_b2b 382.000s 27478.269us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 1376.456us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1887.593us 0 8 0.00
sram_ctrl_throughput_w_readback 12.000s 2653.484us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 24.000s 1631.698us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 5620.531us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 341.000s 113683.837us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 10.917us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 148.725us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 148.725us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 17.684us 1 1 100.00
sram_ctrl_csr_rw 2.000s 133.155us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 65.665us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.039us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 17.684us 1 1 100.00
sram_ctrl_csr_rw 2.000s 133.155us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 65.665us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.039us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 30594.235us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 174.419us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 174.419us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 24.000s 1631.698us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 24.000s 1631.698us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 133.155us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 33.000s 18290.952us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 33.000s 18290.952us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 33.000s 18290.952us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 54.000s 14154.003us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 8316.500us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 30594.235us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 672.890us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 697.905us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 6.000s 697.905us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 33.000s 18290.952us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 54.000s 14154.003us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 6.000s 697.905us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1400.743us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 56.000s 1714.409us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 37704906530325230319191734604878912404077051790813672135388636795768746661465 86
UVM_INFO @ 6566213773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 92620425309602604131534118904044724543537841554958783852309610956034660695852 86
UVM_INFO @ 1887592554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 71902528033009106461604682145733572722864135434062742070832218756198703560022 86
UVM_INFO @ 1376455650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 108993849768961350649401239230697698571548103676172339089348852441791341068342 86
UVM_INFO @ 1402602921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 105731075113743643225820348081289994621870241392839149246878983976728102743019 86
UVM_INFO @ 7328629102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 111784611669015969664297879016664046840381310319179014829773616158242126192101 86
UVM_INFO @ 2781068609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 28331259084836291081990105475421119161000204581231131394984643067195069682419 86
UVM_INFO @ 3881083955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 103638386927305228228245213386644347193053511787058138053721530598988902227216 86
UVM_INFO @ 6610361999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 82190342971560358213471585366925307966274023925883194276667170556211047037376 86
UVM_INFO @ 672875378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 29467017800346894214577589770582967513844495574000399159282768773823116205428 86
UVM_INFO @ 675590809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 86476367396180106919310656442108822551901595843900826603116445204397747254372 86
UVM_INFO @ 673381475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 30537071400753345559823995553067490604394325377786854397400699457621743074578 86
UVM_INFO @ 676483926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 103760514908027717964248158280865115945041646206800907123823990609651294515161 86
UVM_INFO @ 2663310767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25751781622574907819942126336766778448347134403216362798383357298980592554754 86
UVM_INFO @ 678063940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 102821350709690194256160609671700141430273584783458033785554655419213038040876 86
UVM_INFO @ 2641145061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 46783521143823538504442033617867395155199583824402235139602298682765240025629 86
UVM_INFO @ 686211091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 20130952350227919013952447006491844329255805260624446687329567345722942447747 86
UVM_INFO @ 766322314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 61790362815330852940633335342758035308372733389437423295648971659343389436867 86
UVM_INFO @ 2768655324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 82097616912718409253640458885094759835024575151704377660686290271430951503264 86
UVM_INFO @ 663595320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 99530941261997046409181211245981217736278813410743845133637072207791972703423 86
UVM_INFO @ 737740469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 103782273991964518233350517331769697161410872524476192816999825222504149327266 86
UVM_INFO @ 698153725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 17614959035907280249490006494087824202636381984699293007022931517289943738384 86
UVM_INFO @ 2653484088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 114812826697941221550088725270251620037495380666331909022434600170829234868823 86
UVM_INFO @ 668186485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 34528653680951315587004735356081204866723778828896358217693280828563792084014 86
UVM_INFO @ 673831791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---