| V1 |
|
100.00% |
| V2 |
|
98.60% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_smoke | 20 | 20 | 100.00 | |||
| xbar_smoke | 20.130s | 1601.814us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_base_random_sequence | 20 | 20 | 100.00 | |||
| xbar_random | 185.360s | 10274.527us | 20 | 20 | 100.00 | |
| xbar_random_delay | 119 | 120 | 99.17 | |||
| xbar_smoke_zero_delays | 6.600s | 64.248us | 20 | 20 | 100.00 | |
| xbar_smoke_large_delays | 292.220s | 41334.873us | 20 | 20 | 100.00 | |
| xbar_smoke_slow_rsp | 335.610s | 37921.665us | 20 | 20 | 100.00 | |
| xbar_random_zero_delays | 95.320s | 944.026us | 20 | 20 | 100.00 | |
| xbar_random_large_delays | 1311.920s | 116465.898us | 19 | 20 | 95.00 | |
| xbar_random_slow_rsp | 2065.460s | 238667.495us | 20 | 20 | 100.00 | |
| xbar_unmapped_address | 40 | 40 | 100.00 | |||
| xbar_unmapped_addr | 117.950s | 4282.299us | 20 | 20 | 100.00 | |
| xbar_error_and_unmapped_addr | 100.520s | 3730.670us | 20 | 20 | 100.00 | |
| xbar_error_cases | 40 | 40 | 100.00 | |||
| xbar_error_random | 201.890s | 11431.865us | 20 | 20 | 100.00 | |
| xbar_error_and_unmapped_addr | 100.520s | 3730.670us | 20 | 20 | 100.00 | |
| xbar_all_access_same_device | 65 | 70 | 92.86 | |||
| xbar_access_same_device | 355.670s | 11186.213us | 20 | 20 | 100.00 | |
| xbar_access_same_device_slow_rsp | 3185.860s | 372070.942us | 45 | 50 | 90.00 | |
| xbar_all_hosts_use_same_source_id | 20 | 20 | 100.00 | |||
| xbar_same_source | 177.280s | 4897.175us | 20 | 20 | 100.00 | |
| xbar_stress_all | 70 | 70 | 100.00 | |||
| xbar_stress_all | 1173.870s | 71555.194us | 20 | 20 | 100.00 | |
| xbar_stress_all_with_error | 1266.260s | 62120.241us | 50 | 50 | 100.00 | |
| xbar_stress_with_reset | 70 | 70 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 1851.860s | 9740.198us | 20 | 20 | 100.00 | |
| xbar_stress_all_with_reset_error | 1137.140s | 5413.151us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 6 test runs | |||
| xbar_access_same_device_slow_rsp | 89313812544712691974641112842502699580423871531192108759484439864400408046915 | 135 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xbar_random_large_delays | 95451613683426926263864815489028339858264983628495171014880361612635837756565 | 136 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xbar_access_same_device_slow_rsp | 78719505026104262906051180668255268917893195326707172983711373654163739563467 | 180 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xbar_access_same_device_slow_rsp | 5628609829021973428248979746932749635805123062860654901602846336913437000895 | 149 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xbar_access_same_device_slow_rsp | 9963428669638185008360166449112561983285289918876089610582975413962436449524 | 138 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xbar_access_same_device_slow_rsp | 71928254940687671318040119056320584343904078540786980158136902026268179543727 | 168 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|