Simulation Results: ac_range_check

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.58 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
100.00%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 53.000s 3891.103us 20 20 100.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 73.000s 14876.814us 20 20 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 148.235us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 44.647us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 39.000s 717.518us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 21.000s 1418.721us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 26.541us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 44.647us 5 5 100.00
ac_range_check_csr_aliasing 21.000s 1418.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 64.971us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 35.000s 604.169us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 272.000s 61247.754us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 31.000s 16.339us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 15.009us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 125.025us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 125.025us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 148.235us 1 1 100.00
ac_range_check_csr_rw 3.000s 44.647us 5 5 100.00
ac_range_check_csr_aliasing 21.000s 1418.721us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 527.453us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 148.235us 1 1 100.00
ac_range_check_csr_rw 3.000s 44.647us 5 5 100.00
ac_range_check_csr_aliasing 21.000s 1418.721us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 527.453us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 987.704us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 987.704us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 987.704us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 987.704us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 137.000s 5624.951us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 21.516us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 885.997us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 352.000s 2171.513us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 50.000s 6612.455us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo. 1 test run
ac_range_check_stress_all 73710469105674471942961747338032849404741911468907543795110100243652666181214 16365
UVM_INFO @ 100536915924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---