| V1 |
|
100.00% |
| V2 |
|
87.57% |
| V2S |
|
97.56% |
| V3 |
|
30.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 13.450s | 462.521us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 15.760s | 592.957us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 595.330s | 13176.016us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 316.380s | 4263.357us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 18.480s | 165.716us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 15.760s | 592.957us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 316.380s | 4263.357us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 379.880s | 116246.062us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 102.200s | 5855.065us | 50 | 50 | 100.00 | |
| entropy | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.132s | 0.000us | 23 | 25 | 92.00 | |
| sig_int_fail | 48 | 50 | 96.00 | |||
| alert_handler_sig_int_fail | 90.790s | 3419.865us | 48 | 50 | 96.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 86.030s | 9174.709us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 107.020s | 1652.373us | 50 | 50 | 100.00 | |
| ping_timeout | 16 | 50 | 32.00 | |||
| alert_handler_ping_timeout | 619.200s | 16393.888us | 16 | 50 | 32.00 | |
| lpg | 95 | 100 | 95.00 | |||
| alert_handler_lpg | 3600.200s | 0.000us | 49 | 50 | 98.00 | |
| alert_handler_lpg_stub_clk | 3600.138s | 0.000us | 46 | 50 | 92.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 5182.690s | 100008.843us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 39.110s | 870.350us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.000s | 131.723us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.460s | 11.082us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.730s | 860.178us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.730s | 860.178us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 13.450s | 462.521us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 15.760s | 592.957us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 316.380s | 4263.357us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 35.270s | 777.550us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 13.450s | 462.521us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 15.760s | 592.957us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 316.380s | 4263.357us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 35.270s | 777.550us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 447.140s | 41778.084us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 447.140s | 41778.084us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 447.140s | 41778.084us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 447.140s | 41778.084us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1504.600s | 171652.362us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 102.960s | 2501.097us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 102.960s | 2501.097us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 447.140s | 41778.084us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 83.520s | 1678.999us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 48 | 50 | 96.00 | |||
| alert_handler_sig_int_fail | 90.790s | 3419.865us | 48 | 50 | 96.00 | |
| sec_cm_lpg_intersig_mubi | 49 | 50 | 98.00 | |||
| alert_handler_lpg | 3600.200s | 0.000us | 49 | 50 | 98.00 | |
| sec_cm_esc_intersig_diff | 48 | 50 | 96.00 | |||
| alert_handler_sig_int_fail | 90.790s | 3419.865us | 48 | 50 | 96.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.132s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.132s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 209.400s | 5314.134us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 10 | 30.00 | |||
| alert_handler_stress_all_with_rand_reset | 432.270s | 4117.861us | 3 | 10 | 30.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 22 test runs | |||
| alert_handler_ping_timeout | 9068698523345610570127842737288326256660150541602038622659529276263717705473 | 123 |
UVM_INFO @ 46490731821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101687546446539736767422139265541134185606573484890319771554882293795928241030 | 108 |
UVM_INFO @ 17757150155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13772584585212931708406564722607323727470313331296812482008855273247828258247 | 84 |
UVM_INFO @ 1078322310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 62414065218622840691939429410714970257597930764058801156810066751390745897704 | 96 |
UVM_INFO @ 3374922716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51769186124154202557541122567970436270944342948727181122800280251697694762924 | 90 |
UVM_INFO @ 5790353585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 91124459149221004630548933377851529918847046853397296481571926456879102856187 | 109 |
UVM_INFO @ 22416357406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101099114995929565211171425052419927614470588061663274294651009005004109306986 | 87 |
UVM_INFO @ 1643413080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 52109274474561824632759369184712461993234715801443087269537317280796284227869 | 96 |
UVM_INFO @ 10717218205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 11479113365175205877468044742703445396878145914729644516276018730740172637384 | 111 |
UVM_INFO @ 5415067558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 22692091240549815275590251846212654687144127584652410613934512369263191315040 | 126 |
UVM_INFO @ 35995167543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 8838811725347678744952786919407831326081068392156515604739920690894334311078 | 87 |
UVM_INFO @ 4427674204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99202651046825523840499320130175222137818332147309497356631183246314880191308 | 87 |
UVM_INFO @ 797844383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108192801016383423440951902374923617642759199049768044326473614163565707688247 | 130 |
UVM_INFO @ 13255904102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 89201629929020798019487995756788909514197640779716335024587181990735913604919 | 108 |
UVM_INFO @ 4498287309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 46216621036351356465473409425180115120490228063417310949613367526582284175259 | 84 |
UVM_INFO @ 4104395685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 112925870317687114053851458270668307702979825235417307844038604464302181078303 | 139 |
UVM_INFO @ 8193058840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16257364022603847029004715027252803432682337295932054718704186709719798760772 | 111 |
UVM_INFO @ 23956297821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13318203207662415692934516432337850544020766061842442453241880311280368502116 | 84 |
UVM_INFO @ 276108463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 98752128628538549308011265073988504650889681992811187193058789864863405875814 | 93 |
UVM_INFO @ 9680888056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 79204533098591702238642986894073955751430011351175975223188698429729016956694 | 123 |
UVM_INFO @ 33877846903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 17668238084650028842185852681004681719747357419120276191156614377553737994841 | 102 |
UVM_INFO @ 3028519343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 38809348803661315031805548858829988184349800510086438898900567390243772093162 | 126 |
UVM_INFO @ 14232696685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 59175466300382170799852826034675713803128760463722789495365961231318711770491 | 180 |
UVM_INFO @ 292382619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 103749125697895284283213739212850322750528925719359816341239240099856615559447 | 176 |
UVM_INFO @ 163956972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 20920538966973699512511439852170490103358392236281457544234770878087746913253 | 204 |
UVM_INFO @ 356328084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 83005661832728693779218476248221475028560178527164847624151405826336022179486 | 202 |
UVM_INFO @ 1013931615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 24095057834359930485942534478206480421931392580890042723477892747879526831712 | 202 |
UVM_INFO @ 2593656381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 72944184755780278943559014788237330153684080491366471779949174218810720699749 | 216 |
UVM_INFO @ 2009654978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 7434701237140265063550192890116561620653154877731699884795130282050679779234 | 196 |
UVM_INFO @ 478239467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 50609337510963360073394268714935351116810564601770121623577329420451498204276 | 210 |
UVM_INFO @ 127201263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 1252868220265467101500031166251585776054218428190338997837590840643249471289 | 230 |
UVM_INFO @ 471834288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 81770110719593068016003024584681672511125269280748776334066114403872044100142 | 226 |
UVM_INFO @ 1477087229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 92968382985844498465265361260585389764479131421869278368079861561033137262029 | 230 |
UVM_INFO @ 482890568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 65146522484366046835974538820290852027012317021756827883743069995528689443500 | 150 |
UVM_INFO @ 376604945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 69826911565349989863251600439240498301661251645030735029050505605308643618907 | 176 |
UVM_INFO @ 83225386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 65989890079657188238530103089737618538301890907399939487714842713586994514877 | 158 |
UVM_INFO @ 5928789299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 112784808989134511043065085299604081877603436081777132395544261730893733115749 | 180 |
UVM_INFO @ 112093185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 37592300932941698833894912357058286376162118826036807215923847978990594562423 | 188 |
UVM_INFO @ 609958276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 18518208946240570902278413859193354435812849034041685568807873122029086056399 | 228 |
UVM_INFO @ 870349586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 6933711609837056694306140279465168654465112457239100641479823186959965351499 | 222 |
UVM_INFO @ 97289792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 115138427933772347745018718617701725778673351902625888191300084986061038964903 | 154 |
UVM_INFO @ 96419439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51292614282078688649011358432720793552505081239610214115452927309458362368885 | 180 |
UVM_INFO @ 119296124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 11 test runs | |||
| alert_handler_ping_timeout | 82182780320296318332257586040395311651144654438178338107477648464238292463825 | 80 |
UVM_INFO @ 32302603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 95163763910620338196099734691998467280859630408522605928810690741841136053353 | 80 |
UVM_INFO @ 162079823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 52158221414248281557104964664173575836901076418923578831753404602773997697752 | 80 |
UVM_INFO @ 533534805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 101776263727638409962020527057572181932546690855485123260707908668561220758440 | 80 |
UVM_INFO @ 336971655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 75597827294365740100666214205548667199571909520776111588902494900831088030638 | 80 |
UVM_INFO @ 1324484022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 20899621337923726880294057545370707647726240007771903579605317325024868618761 | 80 |
UVM_INFO @ 810635899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 10384137847042625361482067035342375205411495456998918579442232545620192179410 | 80 |
UVM_INFO @ 475569967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 81852963970215822275693236055782564554430988651881145996899300375543994884717 | 81 |
UVM_INFO @ 483163796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 94627185430979675365764157501386562993435958743714364283299610217459729181862 | 80 |
UVM_INFO @ 3745789075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7580113538457831115016528033027852339900165517968623273199329820697681317070 | 80 |
UVM_INFO @ 278690886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 72050669952485578982569137963753565970919597117634014722464067573762709510881 | 80 |
UVM_INFO @ 901814173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 6 test runs | |||
| alert_handler_stress_all_with_rand_reset | 24489532397094574980373640068453906038908281578494441804554714697964510908375 | 180 |
UVM_INFO @ 3665803166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 98640766713616454851519442203893506365963707028676840208396444683548461397126 | 109 |
UVM_INFO @ 7413838549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 267387341816490855232011018225236727304018014743162356104544878383587504686 | 133 |
UVM_INFO @ 1668279248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 92387869233841785362488305515571959649785050875088039150095211685061046458251 | 83 |
UVM_INFO @ 1474976001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 101972044894756622106983830361571922842755816211899052882914196758065011280782 | 101 |
UVM_INFO @ 1464428311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 108023989374528964085306820646780344049113010319349387261728834449227833524743 | 146 |
UVM_INFO @ 2387183091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 6 test runs | |||
| alert_handler_lpg | 8957816421964589721858377653642140022954054154255920264396304938751334126574 | None | ||
| alert_handler_entropy | 65599758665339562492873221717682656841855761875236449992334914035043396185412 | None | ||
| alert_handler_lpg_stub_clk | 94239975092301250269193176984800082024630959098390582438446977183172038413051 | None | ||
| alert_handler_lpg_stub_clk | 80106139741889397859570510200279989718760803928987787962203754790492877558522 | None | ||
| alert_handler_lpg_stub_clk | 7950330703703030749418593719930555644261236806267271325909985244624165419378 | None | ||
| alert_handler_lpg_stub_clk | 68237643287078909207929083723300682139706211269545915695823235330781617809072 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 2 test runs | |||
| alert_handler_sig_int_fail | 64365634890374329815347797535493237717677303703463518396201463863503283799280 | 85 |
UVM_INFO @ 329561995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_sig_int_fail | 88652339803081163503962273091166795920016604206672908987318663393929884063828 | 81 |
UVM_INFO @ 136181052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1199) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| alert_handler_stress_all_with_rand_reset | 59693981803514129796745985188186709599212166855441993445340647100598013353629 | 136 |
UVM_INFO @ 1044669879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_entropy | 86643016986401787774338291724504863706465747953986307390424405815615878922006 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalAlertPingFail) | 1 test run | |||
| alert_handler_ping_timeout | 48870671169402920333789975010102365095652118514227803314358032629652297128098 | 99 |
UVM_INFO @ 2519874678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|