Simulation Results

Simulation Results: clkmgr

24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.65 %

code
69.16 %

assert
90.08 %

func
73.71 %

line
81.76 %

branch
86.53 %

cond
79.79 %

toggle
97.74 %

FSM
0.00 %

Validation stages

V1		73.91%
V2		69.23%
V2S		29.52%
V3		0.00%

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	1.800s	49.287us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.200s	22.025us	1	1	100.00
csr_rw				3	5	60.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.830s	46.039us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.150s	8.782us	0	1	0.00
csr_mem_rw_with_rand_reset				3	5	60.00
	clkmgr_csr_mem_rw_with_rand_reset	3.370s	135.076us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
	clkmgr_csr_aliasing	1.150s	8.782us	0	1	0.00

81/117 passed

69.23 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	3.360s	210.859us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.730s	188.115us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	3.130s	169.785us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	1.800s	49.287us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.100s	14.783us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.040s	11.368us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.100s	14.783us	0	10	0.00
stress_all				2	10	20.00
	clkmgr_stress_all	8.410s	750.089us	2	10	20.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.180s	83.681us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	10.060s	544.740us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	10.060s	544.740us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.200s	22.025us	1	1	100.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
	clkmgr_csr_aliasing	1.150s	8.782us	0	1	0.00
	clkmgr_same_csr_outstanding	2.530s	107.662us	0	5	0.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.200s	22.025us	1	1	100.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
	clkmgr_csr_aliasing	1.150s	8.782us	0	1	0.00
	clkmgr_same_csr_outstanding	2.530s	107.662us	0	5	0.00

V2S

31/105 passed

29.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	clkmgr_sec_cm	2.210s	78.843us	0	5	0.00
	clkmgr_tl_intg_err	2.320s	85.571us	0	25	0.00
shadow_reg_update_error				18	20	90.00
	clkmgr_shadow_reg_errors	1949.550s	200000.000us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	clkmgr_shadow_reg_errors	1949.550s	200000.000us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	clkmgr_shadow_reg_errors	1949.550s	200000.000us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	clkmgr_shadow_reg_errors	1949.550s	200000.000us	18	20	90.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.680s	49.265us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.320s	85.571us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.100s	14.783us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.040s	11.368us	0	10	0.00
sec_cm_meas_config_shadow				18	20	90.00
	clkmgr_shadow_reg_errors	1949.550s	200000.000us	18	20	90.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.210s	79.358us	10	10	100.00
sec_cm_jitter_config_mubi				3	5	60.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	2.210s	78.843us	0	5	0.00
sec_cm_meas_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
sec_cm_clk_ctrl_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.350s	32.432us	3	5	60.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	2.210s	78.843us	0	5	0.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.040s	9.620us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	4.390s	146.219us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				26 test runs
	clkmgr_csr_rw	95632333812790555298524049106392160852644862966857206149953255894589550149359	76	UVM_INFO @ 7616464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	52150998051452834198146135589138159584807893227417983123793103487040912283402	75	UVM_INFO @ 8782456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	38397447432217607318913738005402104951388916266795147151786009029038874363550	76	UVM_INFO @ 135075971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	56614866876914520657178349428539912167479852113014895260652824694597552343718	75	UVM_INFO @ 2487999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	124996536819637929691064998312171185552664946215463457764562131327486066521	102	UVM_INFO @ 29463166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	3679652417763952216907451194108566960500636709415044087420126176615013009946	78	UVM_INFO @ 4022013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	54490407324419439574594851199436660054242393488680911740820121564067803855834	75	UVM_INFO @ 7180410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76133037746511430136837295814424292329908149707757383764384726182826089223670	75	UVM_INFO @ 19557605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	94033792962265548048013806036455460908631426782436303000142379416826285164339	78	UVM_INFO @ 5030646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	104211224624470555776900442789571781644881326485541747719699736538458962549404	75	UVM_INFO @ 5190091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	47009496784726070604397820641506673215391925867176332947299125866301496839027	86	UVM_INFO @ 8892235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3323836636127868342674425986029553181373639030067745562504122550879065134183	75	UVM_INFO @ 14535217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	14286437833119940805002316824887439383512514045002453596174312809275273524900	75	UVM_INFO @ 6712590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	35245891791254282879662719644582635614569448839844920076759157540656080454435	75	UVM_INFO @ 3521517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	20858116013257738921545876847281779750621589226489452456313974916085133124963	89	UVM_INFO @ 49470779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	5226516823076275750548800662379984249504574136309908702386679326852468876381	75	UVM_INFO @ 6788760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83569888812839112916402963569932169049628587052260187979551817151731117415750	86	UVM_INFO @ 9160105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	85674114891805177387617381018699071209024921720030892068369205910472300198563	75	UVM_INFO @ 36968813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	93690536394812879263540253373862204079755930856183498333493722263472614993510	75	UVM_INFO @ 7412867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	113615864705371064826271965113499736572532227761044994423367009539421866963836	75	UVM_INFO @ 2817249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	9371253601172782776802014555469158909265491451970139856892811630774428635640	75	UVM_INFO @ 11404268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	12872357971140713864800378868365771091349952370242746856325810855299964020456	85	UVM_INFO @ 5722711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	60874665756294738221717296973695184015775876841395223967595218115406085654226	75	UVM_INFO @ 49264680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	23823225571281215684097023632453738528391235148797499263923641512724392363848	78	UVM_INFO @ 7756925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	54842706557998176868806961450487628807314131426808654935105640403070209174436	93	UVM_INFO @ 9032457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	103785820187232770912045170877438369911878484656965736509480478729291144637773	82	UVM_INFO @ 4928750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				24 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	85771455699432601423535863467337980975676763351007083381472063436300279698373	75	UVM_INFO @ 15895573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	39017284573214370409568340480612886470470172207859357647132028709380641276451	89	UVM_INFO @ 21634774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	34627537072754262039944986706309267307471763346569881863373182518080833960938	82	UVM_INFO @ 11195841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	43381971393188105473818920343820376107372517629967508877667759729683168977301	75	UVM_INFO @ 10514179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	104769088619400895225448202957365120654031159261835276717036585493129643330888	115	UVM_INFO @ 85570661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	13778035173381129133818857053021544274151644467536808873308252122749583096827	75	UVM_INFO @ 3446587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	83800915841408122922266392228397329444292845747251651217244540904325870248995	93	UVM_INFO @ 49613617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	34711405158508805029652060297950880680018197015043710966204773954010273130756	78	UVM_INFO @ 6619576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106847772843774608634506770696659877304997150018079999134060632284533880856910	79	UVM_INFO @ 8941683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	104034049117044415403674938343332471679304884980370194294046296736858814713744	75	UVM_INFO @ 7717138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	55611788698920229626353866609987266499650136155201347921334873585703986982681	75	UVM_INFO @ 6031406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31707803266605634835581735084305907766308486151285217612554481795777447941855	83	UVM_INFO @ 14830987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76584720130868535333622678970907086714499097288791165763923474663896361015557	75	UVM_INFO @ 5723087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	68041983989882045849543855463328695177524594782615416302995729433125730353482	112	UVM_INFO @ 72155014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31663543353308222350753915620884710993694962150005102015705679380776189838007	85	UVM_INFO @ 5281741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	92613622885752199760290696719813255095277784556120214106699351101779632968601	75	UVM_INFO @ 2970178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86920764385089738405494298753929188225308193471667296925219368182039305490031	75	UVM_INFO @ 11444284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	55799196121061792176475478169562133156565115240955689525006963135787777231770	89	UVM_INFO @ 13169586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	48280887826620967609913485812283821556062616248369404000235180714616912793885	85	UVM_INFO @ 11644845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	47084440340460232954707038989918360247034848177253325643513510246908901198015	78	UVM_INFO @ 11861415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	114980157153163566754520060319583540854994470181744729429116076922853454853847	101	UVM_INFO @ 58257625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	54781941116939233692465879072771416389355402723823653634428009419394678840831	96	UVM_INFO @ 19760397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	101907337767964029034426362693129417528498974994279387827298234732814674179433	86	UVM_INFO @ 10585469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24792477705339956119758377639583599021781118903797226378164604493866637091188	86	UVM_INFO @ 9746254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				20 test runs
	clkmgr_frequency_timeout	3418408268045079985270285418902444593666197798891924899083371403261533861782	78	UVM_INFO @ 3750312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	26650578892066953789197195717275468184612582649562062595663897305734483895838	78	UVM_INFO @ 5780415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	2453344107997645819797311624500185225781713295460960181445771031981246040118	78	UVM_INFO @ 6403504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	40271637438939684372500582822731683263122377431440581489284105915961432464206	77	UVM_INFO @ 4770671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	26218214865175301868829582299696777501703590283095510181159996830218541258178	78	UVM_INFO @ 2815517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	49456602594820593931651911007872697712406021328651238669290976701873635836297	77	UVM_INFO @ 3428906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	63036595255676169109225330792141412437994586958771871675063752739613045939852	79	UVM_INFO @ 28103273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	85371479588322877858743779310555945500484537780798209453011000396642141511762	78	UVM_INFO @ 5747039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	101048166721215211217172405380663038064985537183031681856862565921590847868599	78	UVM_INFO @ 58512698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	63598278206384690111453419175504264958998823989668708767328630257356853033042	77	UVM_INFO @ 3439819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	76452358122613913092644315969268316276400009158385146167121437556972605084452	79	UVM_INFO @ 7748643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	35079721890718990755103639701990349773365113860291709202702378789895448031695	134	UVM_INFO @ 100023929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	103530733495296963387090177757174963667235402185549188224924308709681499445547	78	UVM_INFO @ 11367683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	21987500828099600626466757076218471452561353214631352480130446166666510960512	113	UVM_INFO @ 146218542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	2305580708988422680853885323900556922447606207924414430211580220782537813526	78	UVM_INFO @ 46251176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	23547952062549800944428890466797830871535239104115330803275826438633568910166	78	UVM_INFO @ 3453507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	7881575501421184051218092189390441082741918442065739398018943644876398024302	79	UVM_INFO @ 4426535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	91417444855443008851592746721588810277332398587877909340569711520660743735151	78	UVM_INFO @ 2795123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	62032784104118479771625593223400795029734028078747003126911441009743884040974	79	UVM_INFO @ 103262218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	115278389197592740982866060312219336868815782596527568067176493504586323719610	78	UVM_INFO @ 10731388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				18 test runs
	clkmgr_frequency	112057055168158012505420377116702660570394026977439082580880011719473539708431	75	UVM_INFO @ 14983606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	32113424165706031051650088040544083170377879922193545415269574089620242228058	77	UVM_INFO @ 10132944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	88256488238289297812288355563137893178222740818887862974489462510338600521060	75	UVM_INFO @ 14782558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	75675776920955100139499888061426511123670888410001290404969612053731617990299	153	UVM_INFO @ 101140756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	28480302808711864794342439101403423801848990274468032553988881501743842863834	75	UVM_INFO @ 6788197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	99438948188047641129312777286213425840058763981304556850694808399343360284543	105	UVM_INFO @ 79040370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	16504511946100006841263763266446627093780892753177069225091951993922044824564	88	UVM_INFO @ 205705304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	94853808804036076204152407669059478404093793175355165876769163034533162115723	75	UVM_INFO @ 4870391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	99826499733689990797301401230283572479594554381723129711800142266680333621838	78	UVM_INFO @ 13067596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	86441424817737906574693818748045515374677454296370522127841045654107760557261	77	UVM_INFO @ 132120185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	43795326542937059829126020100269942838679077263527080270434484403197677988329	75	UVM_INFO @ 13664320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	11073333706922378321212169670554992469710192210545762595212935137160233792915	76	UVM_INFO @ 6034144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	17719591187411885473774139856571918863918661437382860525554949974889402274566	84	UVM_INFO @ 32554389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	93830945662662960954104149624775711798039378302543068957222443644564933850768	76	UVM_INFO @ 9248130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	53298916895745534630149381850846406080249861765684967272563407855809242717765	75	UVM_INFO @ 8064052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	17362913866169122721080042299791640971095039643705969536427235048952962516064	76	UVM_INFO @ 10009464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	43313302374216390456821243088805594513745239669193994987806060871644637649367	75	UVM_INFO @ 25502161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	75853048041522131915663791019088024831368324442710760839006949135691831764904	75	UVM_INFO @ 14608209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				7 test runs
	clkmgr_regwen	26696469064036117539185613734008336574688660841363674324816613926738964486285	74	UVM_INFO @ 5657486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	105861306600069308447605288931953552424869807603866960573031863215981338373453	74	UVM_INFO @ 9619633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	2658432651721808932290939231526344206038598722822799995045637198581814225464	74	UVM_INFO @ 4396896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	43341082580056423857587894051697927766597257111898584736905896153824725057008	74	UVM_INFO @ 5218620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	43928854554638826070941672800594398305094184155828505640310529776413156583984	74	UVM_INFO @ 4176889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	37858321180339473701541242351902349173147366544824384403422623005085580535618	74	UVM_INFO @ 5960322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	95591623462658406316431775069115178973106953872615211835124885875988403319506	74	UVM_INFO @ 2852955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				5 test runs
	clkmgr_sec_cm	25215506699983233919811919391295993720865467919297289883480559102897931642222	114	UVM_INFO @ 78843199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	15845378446236569598878973522939619705336507167962995865621166331338445803691	83	UVM_INFO @ 6186316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	62384608743644493291132354544620822074665048808185278260669536577277665044624	86	UVM_INFO @ 33637482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	64131740154702252190056180954681420497330224659655495195641913702753482953075	97	UVM_INFO @ 24387788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	28885783329668441882949943541529736688413605164952380956051659356947894690817	80	UVM_INFO @ 5411650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	113440360294666222465237790343852427780558098249344562985674639488090778862785	75	UVM_INFO @ 18584523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	53813191068810359388466227258805428505360158993108920700849623388045873529469	75	UVM_INFO @ 37833292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	35499024808410973180096386812988950112045557931157753516705553373992921718361	75	UVM_INFO @ 6936576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	55098568635336092911830928115665384408737308034081760677166215354330060150798	75	UVM_INFO @ 107661519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	71475780174102202372622713641603347160266789348479329877615741913715088473728	75	UVM_INFO @ 4309204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				3 test runs
	clkmgr_regwen	4837912798223844507928626624937136246961240881181704776096471634002666137916	74	UVM_INFO @ 3036009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	40142089162971767899412608761544683374045838917085697649233142217457888685156	74	UVM_INFO @ 7829251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	82977554549221939785027794504222401137160490835165928078196672721647387839469	74	UVM_INFO @ 3623833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	clkmgr_shadow_reg_errors	95732833305437823781791645567737320967277484115562396183164470158315319516006	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	106404919457383261519045498732415292429977895410894057234484245549999155859336	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	87468943687037366772237662958044890969079906333026999037406121660707549232901	75	UVM_INFO @ 46039066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---