Simulation Results

Simulation Results: csrng

24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.63 %

code
96.20 %

assert
96.94 %

func
90.74 %

block
98.53 %

line
99.54 %

branch
96.38 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.01%
V2S		99.07%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	4.000s	84.569us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	32.000s	33.499us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	32.000s	15.187us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	45.000s	299.889us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	34.000s	76.441us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	32.000s	14.255us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	32.000s	15.187us	5	5	100.00
	csrng_csr_aliasing	34.000s	76.441us	1	1	100.00

1281/1307 passed

98.01 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	95.000s	7142.887us	500	500	100.00
err				500	500	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
cmds				1	25	4.00
	csrng_cmds	98.000s	2774.652us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	98.000s	2774.652us	1	25	4.00
stress_all				23	25	92.00
	csrng_stress_all	581.000s	11415.825us	23	25	92.00
intr_test				10	10	100.00
	csrng_intr_test	3.000s	14.068us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	32.000s	33.278us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	16.000s	627.685us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	16.000s	627.685us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	33.499us	1	1	100.00
	csrng_csr_rw	32.000s	15.187us	5	5	100.00
	csrng_csr_aliasing	34.000s	76.441us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	80.789us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	33.499us	1	1	100.00
	csrng_csr_rw	32.000s	15.187us	5	5	100.00
	csrng_csr_aliasing	34.000s	76.441us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	80.789us	5	5	100.00

V2S

1273/1285 passed

99.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
	csrng_tl_intg_err	11.000s	731.251us	25	25	100.00
sec_cm_config_regwen				20	30	66.67
	csrng_regwen	4.000s	185.348us	15	25	60.00
	csrng_csr_rw	32.000s	15.187us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	95.000s	7142.887us	500	500	100.00
sec_cm_intersig_mubi				23	25	92.00
	csrng_stress_all	581.000s	11415.825us	23	25	92.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	95.000s	7142.887us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
sec_cm_constants_lc_gated				23	25	92.00
	csrng_stress_all	581.000s	11415.825us	23	25	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	95.000s	7142.887us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	11.000s	731.251us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00
	csrng_sec_cm	5.000s	163.506us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	44.000s	706.094us	200	200	100.00
	csrng_err	32.000s	77.181us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				23 test runs
	csrng_cmds	25565184440986984320155139973644562610383674906381081648160193171963201817744	100	UVM_INFO @ 165813327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41639201695500856487655421011954848490348011766634229825283896004016302452380	100	UVM_INFO @ 152584720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	12855934786435346713917165992363894651880389840782775740474614944147390047200	100	UVM_INFO @ 294486981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13055748622332619488362252298940278344501086223597479256403868980778267220787	100	UVM_INFO @ 191142801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35435416534582319621281470841547912600366382866417625447814136420887436227285	100	UVM_INFO @ 148586162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	71293541828349048083364768706210621168246353054282433324617815275556553036270	100	UVM_INFO @ 94612710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	102445942201540280746622344196092780179373354035985623892127942969723017846511	110	UVM_INFO @ 125936531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	72924670961955243466460585454005876378577358607522833100356384770314840360239	100	UVM_INFO @ 73622351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	28160631811730954935301861860307893301177604330483426156227977891142644802403	100	UVM_INFO @ 160191657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38068598753338323990050851114480512622228061123655300843581223859703926993710	100	UVM_INFO @ 18556534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88353046701486614858408344823380205477356459948354563991842001649174080723487	100	UVM_INFO @ 321716078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	74918136541807556050508139875571686584024171028382393085634991851802837304368	110	UVM_INFO @ 151372984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15222884707821973653022522198854883329262148968803149821940295061020932180836	100	UVM_INFO @ 41974854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51041572042244575685456194195407716611405483978590152926534985495683697123862	100	UVM_INFO @ 5710360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67114829270675397582798125477260367807225140397616808582128467244193898745394	100	UVM_INFO @ 81340948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24800771355780320947727955276889082436703865374778719395570110747597340405701	100	UVM_INFO @ 180537666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105521864143782983498567263058133569669643409750847408071288638861962180638467	100	UVM_INFO @ 96793098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6255672868180242971505088115999004046285826552640827741055262132817293316026	100	UVM_INFO @ 379310807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35315585379524060745242189878306187266244954394411099686243637068515521694611	100	UVM_INFO @ 41423145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91037047449125024719052721426760425652349100107326494616426519458157754725093	100	UVM_INFO @ 100137148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92860813412129196902952886112350013604109369756270581563893846087883031201459	100	UVM_INFO @ 80379589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	59875198780951574377976570497168377692106239928649397774790968488856708179002	100	UVM_INFO @ 28074428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31556750268800589021112733489933856314646951422049356202602069950323338137925	100	UVM_INFO @ 12619576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				8 test runs
	csrng_regwen	94289413137813471308935460959267695280466482716949389715325685384317504778021	99	UVM_INFO @ 3624372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	115074485717408315645515859894795309230120821011078098931078215289416993388247	99	UVM_INFO @ 3385051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	42946376293317121871160066057012688605095345224623977495459747784504593056784	99	UVM_INFO @ 38690139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	32117125883183818698621435275568595329323647051506926589812882218157900790549	99	UVM_INFO @ 1242667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	20488307832594151544014535143165895940571424304441613168019574517123793729915	99	UVM_INFO @ 20588502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	32007777153490642804259350338612726461733384664938032376205157100318298474667	99	UVM_INFO @ 1672155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	34092512215054948548872384994771301886166822343098010757981665383745898454034	99	UVM_INFO @ 5920932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	24767063666121791299205933751300664743600062776006031021676409422577943516602	99	UVM_INFO @ 6346117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	csrng_stress_all_with_rand_reset	46495658372457315943571542773995844232636243374199733050781674005407938708322	None
	csrng_stress_all_with_rand_reset	95806523874705097107174444622171443337513360090545642518081351515261754752286	None
	csrng_stress_all_with_rand_reset	43032132292317870190539985642547633278618744115507448058672182407487681660280	None
	csrng_stress_all_with_rand_reset	90598298429355112361886413387612798842298191598291989781269085634555266567014	None
	csrng_stress_all_with_rand_reset	106259457054507034762844431127294334411298559462514926080026293035438786952231	None
	csrng_stress_all_with_rand_reset	113660225097007673112328544493742081335190553268891522853332593020617995933488	None
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all_with_rand_reset	88419992169783063154946645023791237885992745171981134591962170862723427997219	184	UVM_INFO @ 369366435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	83834255765008075620286563584562223623238339732373668097305068073106195340935	107	UVM_INFO @ 5660783483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	33095930852041501011006944820391105989124059818440149169796243614952838200230	107	UVM_INFO @ 3191970759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				2 test runs
	csrng_stress_all_with_rand_reset	89769300551441603372344041233088784348250111739391633721866349846691786838960	233	UVM_INFO @ 4489542671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	47190440874578632211824021164215131409416886782600265882823798801683831788020	113	UVM_INFO @ 1334514044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				2 test runs
	csrng_regwen	10937479352967071356554940858673109017456953457138203095544929752309784969874	99	UVM_INFO @ 5449320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	90477271632133273563259965068422132919635609665740297711473780374378526829601	99	UVM_INFO @ 5861316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	102823927203150906431459617810150408146941192644572661249808061319004276183292	117	UVM_INFO @ 348997337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				1 test run
	csrng_cmds	44183057574587971586986592650256771245374717682763003036584722819689332288245	109	UVM_INFO @ 69430770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---