Simulation Results: dma

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.13 %
  • code
  • 90.41 %
  • assert
  • 96.61 %
  • func
  • 80.36 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
93.55%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 12.000s 3509.752us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 1348.256us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 10.000s 1601.347us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 18.641us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 72.423us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 8.000s 282.384us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 532.780us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 37.143us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 72.423us 5 5 100.00
dma_csr_aliasing 4.000s 532.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 65.000s 3808.826us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1253.000s 86586.559us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 2532.000s 181087.257us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 2532.000s 181087.257us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1253.000s 86586.559us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1240.000s 162510.542us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 2532.000s 181087.257us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 19.000s 1049.825us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 311.000s 75212.372us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 12.352us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 93.881us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 5.000s 184.286us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 5.000s 184.286us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 1.000s 18.641us 1 1 100.00
dma_csr_rw 2.000s 72.423us 5 5 100.00
dma_csr_aliasing 4.000s 532.780us 1 1 100.00
dma_same_csr_outstanding 3.000s 106.145us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 1.000s 18.641us 1 1 100.00
dma_csr_rw 2.000s 72.423us 5 5 100.00
dma_csr_aliasing 4.000s 532.780us 1 1 100.00
dma_same_csr_outstanding 3.000s 106.145us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 30.000s 4386.485us 5 5 100.00
dma_generic_stress 1240.000s 162510.542us 5 5 100.00
dma_handshake_stress 2532.000s 181087.257us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 13.000s 376.155us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 389.154us 25 25 100.00
dma_sec_cm 2.000s 13.531us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 29 31 93.55
dma_short_transfer 195.000s 37267.227us 24 25 96.00
dma_longer_transfer 26.000s 694.696us 5 5 100.00
dma_stress_all_with_rand_reset 3.000s 112.207us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 615240219583861036607393850941657181201042949076516153730649269743805441314 92
UVM_INFO @ 112206619ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue 1 test run
dma_short_transfer 35445008183313434925063202124476869098058581379891656632038578093490627209545 2163
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---