Simulation Results: edn/edn0

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.14 %
  • code
  • 95.28 %
  • assert
  • 98.67 %
  • func
  • 58.46 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 16.546us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 83.374us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 159.678us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 84.595us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 32.533us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 7.000s 24.093us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 159.678us 5 5 100.00
edn_csr_aliasing 2.000s 32.533us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 7.000s 1180.339us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 7.000s 1180.339us 100 100 100.00
genbits 100 100 100.00
edn_genbits 7.000s 1180.339us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 29.040us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 61.138us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 34.282us 100 100 100.00
disable 92 100 92.00
edn_disable 2.000s 30.090us 50 50 100.00
edn_disable_auto_req_mode 19.000s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 8.000s 363.090us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 21.312us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 42.229us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 132.661us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 132.661us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 83.374us 1 1 100.00
edn_csr_rw 2.000s 159.678us 5 5 100.00
edn_csr_aliasing 2.000s 32.533us 1 1 100.00
edn_same_csr_outstanding 3.000s 63.587us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 83.374us 1 1 100.00
edn_csr_rw 2.000s 159.678us 5 5 100.00
edn_csr_aliasing 2.000s 32.533us 1 1 100.00
edn_same_csr_outstanding 3.000s 63.587us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
edn_tl_intg_err 4.000s 270.028us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 54.178us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 61.138us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 61.138us 200 200 100.00
edn_sec_cm 10.000s 5434.112us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 61.138us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 270.028us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 120.000s 4821.269us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 39872802553946733498638177884016077827658333380005278364129463236550253627512 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78202113730724110949590456931031242853141668259161475294072915741701407047120 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65540611069208813644939067698894269721264105815114248076209784329422340761029 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 4247190867822511423048112875745728129463267347436276343341485938866492372986 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 49220801353464384498085846460656138728496459370640313626688372124933099119577 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 1519014791934330313292058635025004509654641503837735536723577381671876845301 334
UVM_INFO @ 4821269283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 54019217796549996362135892199563604357749000201986308790489356378017665568803 401
UVM_INFO @ 2876829358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 15604523836969847922206409595984053991717671894531369119312877036721524462896 155
UVM_INFO @ 990726510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 28135194833070877983373302461074337242364111637244011388715223090952916752844 249
UVM_INFO @ 1993896507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 110867167066031526494085290795736804199128211229600260279394078274362771323811 103
UVM_INFO @ 38261154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78876074602754578279756106299587539399928526506018866093724427368554041817961 103
UVM_INFO @ 13303363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 77367046423516695607179014911153587280378819873779815480143293040213993910950 103
UVM_INFO @ 80821989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 37006785847923938989699952501850033105345458036574199541369940226181202802652 210
UVM_INFO @ 11799439128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---