Simulation Results: edn/edn1

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.34 %
  • code
  • 95.87 %
  • assert
  • 97.92 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.08 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.290s 56.332us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.020s 31.116us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.240s 48.140us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.230s 441.668us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 16.357us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.560s 45.690us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.240s 48.140us 5 5 100.00
edn_csr_aliasing 1.080s 16.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 71.530s 4368.461us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 71.530s 4368.461us 100 100 100.00
genbits 100 100 100.00
edn_genbits 71.530s 4368.461us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.300s 20.808us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.750s 160.617us 200 200 100.00
errs 100 100 100.00
edn_err 1.510s 47.672us 100 100 100.00
disable 94 100 94.00
edn_disable 1.180s 53.756us 50 50 100.00
edn_disable_auto_req_mode 2.200s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 6.090s 1664.218us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.220s 53.416us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.120s 41.527us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.340s 131.017us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.340s 131.017us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.020s 31.116us 1 1 100.00
edn_csr_rw 1.240s 48.140us 5 5 100.00
edn_csr_aliasing 1.080s 16.357us 1 1 100.00
edn_same_csr_outstanding 1.480s 40.216us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.020s 31.116us 1 1 100.00
edn_csr_rw 1.240s 48.140us 5 5 100.00
edn_csr_aliasing 1.080s 16.357us 1 1 100.00
edn_same_csr_outstanding 1.480s 40.216us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
edn_tl_intg_err 3.860s 258.341us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.120s 56.094us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.750s 160.617us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.750s 160.617us 200 200 100.00
edn_sec_cm 4.260s 680.639us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.750s 160.617us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.860s 258.341us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 79.920s 8268.756us 27 30 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 94222611082093573594284448911154844189456584853438618867727349788528022441512 145
UVM_INFO @ 1150646211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 95332703101529608625266156048135436871683528080519114933058308147375244715687 199
UVM_INFO @ 2641337568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 86525352744522434972448535492968546468183733364899533426453153924912033328398 137
UVM_INFO @ 1026443905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 74388550766684311439308496250461478258684459914452628445973949113483764796383 88
UVM_INFO @ 16035906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 86008895647151236538522466494000290203443927437205086871773124085076793625401 88
UVM_INFO @ 29753570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 24375576886677114466853958679397803754950246139792981798753481633600034908301 88
UVM_INFO @ 28750586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 29454282755026060310316062476336835531222478403995975977632968271101391277903 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109600531305661504462371247588035968331384600825230998194511771354272063079046 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106247165358977612577606791564413086652855644925737254939856483549438000904578 90
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---