Simulation Results: hmac

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 19.000s 1349.703us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 131.087us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 29.487us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.000s 5659.284us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.000s 422.690us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1084.000s 215411.017us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 29.487us 5 5 100.00
hmac_csr_aliasing 4.000s 422.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 69.000s 23250.926us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 102.000s 4717.259us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 346.000s 10396.687us 30 30 100.00
hmac_test_sha384_vectors 688.000s 39652.773us 75 75 100.00
hmac_test_sha512_vectors 724.000s 41243.892us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 556.841us 50 50 100.00
hmac_test_hmac384_vectors 32.000s 1884.440us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 543.634us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 47.000s 3976.343us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 397.000s 92852.603us 10 10 100.00
error 10 10 100.00
hmac_error 99.000s 42550.898us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 180.000s 11807.924us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 19.000s 1349.703us 10 10 100.00
hmac_long_msg 69.000s 23250.926us 10 10 100.00
hmac_back_pressure 102.000s 4717.259us 25 25 100.00
hmac_datapath_stress 397.000s 92852.603us 10 10 100.00
hmac_burst_wr 47.000s 3976.343us 50 50 100.00
hmac_stress_all 1132.000s 420289.596us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 19.000s 1349.703us 10 10 100.00
hmac_long_msg 69.000s 23250.926us 10 10 100.00
hmac_back_pressure 102.000s 4717.259us 25 25 100.00
hmac_datapath_stress 397.000s 92852.603us 10 10 100.00
hmac_wipe_secret 180.000s 11807.924us 10 10 100.00
hmac_test_sha256_vectors 346.000s 10396.687us 30 30 100.00
hmac_test_sha384_vectors 688.000s 39652.773us 75 75 100.00
hmac_test_sha512_vectors 724.000s 41243.892us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 556.841us 50 50 100.00
hmac_test_hmac384_vectors 32.000s 1884.440us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 543.634us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 19.000s 1349.703us 10 10 100.00
hmac_long_msg 69.000s 23250.926us 10 10 100.00
hmac_back_pressure 102.000s 4717.259us 25 25 100.00
hmac_datapath_stress 397.000s 92852.603us 10 10 100.00
hmac_burst_wr 47.000s 3976.343us 50 50 100.00
hmac_error 99.000s 42550.898us 10 10 100.00
hmac_wipe_secret 180.000s 11807.924us 10 10 100.00
hmac_test_sha256_vectors 346.000s 10396.687us 30 30 100.00
hmac_test_sha384_vectors 688.000s 39652.773us 75 75 100.00
hmac_test_sha512_vectors 724.000s 41243.892us 75 75 100.00
hmac_test_hmac256_vectors 32.000s 556.841us 50 50 100.00
hmac_test_hmac384_vectors 32.000s 1884.440us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 543.634us 75 75 100.00
hmac_stress_all 1132.000s 420289.596us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1132.000s 420289.596us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 13.152us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 3.000s 169.949us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 226.162us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 226.162us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 131.087us 1 1 100.00
hmac_csr_rw 2.000s 29.487us 5 5 100.00
hmac_csr_aliasing 4.000s 422.690us 1 1 100.00
hmac_same_csr_outstanding 4.000s 151.525us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 131.087us 1 1 100.00
hmac_csr_rw 2.000s 29.487us 5 5 100.00
hmac_csr_aliasing 4.000s 422.690us 1 1 100.00
hmac_same_csr_outstanding 4.000s 151.525us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 174.139us 5 5 100.00
hmac_tl_intg_err 6.000s 343.331us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 343.331us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 19.000s 1349.703us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 20.000s 114.247us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 366.000s 281453.302us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 9.459us 1 1 100.00