Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.98 %
  • code
  • 93.20 %
  • assert
  • 96.40 %
  • func
  • 89.35 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.33%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 93.018us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 22.000s 15.650us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 9.000s 18.886us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 23.000s 101.171us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 22.000s 137.650us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 10.000s 77.436us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 9.000s 18.886us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 137.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 115.680us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 1663.386us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 22.000s 13.876us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 155.521us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 16.000s 4170.568us 20 20 100.00
security_escalation 137 140 97.86
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_prog_failure 4.000s 155.521us 20 20 100.00
lc_ctrl_errors 16.000s 4170.568us 20 20 100.00
lc_ctrl_security_escalation 8.000s 824.820us 20 20 100.00
lc_ctrl_jtag_state_failure 33.000s 8014.578us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 5840.786us 18 20 90.00
lc_ctrl_jtag_errors 37.000s 17082.758us 20 20 100.00
jtag_access 207 210 98.57
lc_ctrl_jtag_smoke 5.000s 1097.840us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 4302.513us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 5840.786us 18 20 90.00
lc_ctrl_jtag_errors 37.000s 17082.758us 20 20 100.00
lc_ctrl_jtag_access 12.000s 1448.421us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 5782.709us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 76.312us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 1827.343us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 5532.430us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 7725.871us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 85.685us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 1573.991us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 129.545us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 7.000s 968.628us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 46.293us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 118.000s 263730.356us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 22.000s 83.664us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 291.852us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 291.852us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 22.000s 15.650us 1 1 100.00
lc_ctrl_csr_rw 9.000s 18.886us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 137.650us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 48.507us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 22.000s 15.650us 1 1 100.00
lc_ctrl_csr_rw 9.000s 18.886us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 137.650us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 48.507us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 141.296us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 141.296us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 9.000s 1663.386us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 2028.878us 20 20 100.00
lc_ctrl_sec_cm 5.000s 1303.432us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.000s 824.820us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 115.680us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 4302.513us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 485.651us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 485.651us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 1630.621us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 1528.806us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 1528.806us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 52.000s 3655.428us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 87997907351776423699642325149637432299440055417323210234451900160702349087898 675
UVM_INFO @ 8432494266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64552947198702096295515786835077429908141835743970445218233346587339745068729 161
UVM_INFO @ 215995103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109005711686634308818413448418226658927369532513765828520933384430123568084417 161
UVM_INFO @ 431291240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32495564348125047325906387479058256295825976759718290152510613115522118004827 1101
UVM_INFO @ 6730562694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12151406305226028296981205518436604445326605272555352095063362622481664701466 2140
UVM_INFO @ 3754653603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_prog_failure 11027537587503957435546028509780248247568679934578502088893393481976311585743 177
UVM_INFO @ 83698587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 102499351311920148716593693806137698632098745091055078115763245086865526637940 176
UVM_INFO @ 467090197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_post_trans 88425467536071682861416208499848008948857586903345437817975228094317246637882 178
UVM_INFO @ 382141289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 3566277480113369193742697216030840677439310023100656782834843554123314156301 178
UVM_INFO @ 145407063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---