Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.91 %
  • code
  • 94.15 %
  • assert
  • 96.83 %
  • func
  • 87.74 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.30%
V2S
99.33%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 155.194us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 30.416us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 40.843us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 1163.028us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 106.068us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 138.176us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 40.843us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 106.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 200.457us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1585.016us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 58.882us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 601.959us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 8.000s 619.741us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_prog_failure 4.000s 601.959us 20 20 100.00
lc_ctrl_errors 8.000s 619.741us 19 20 95.00
lc_ctrl_security_escalation 8.000s 9731.605us 20 20 100.00
lc_ctrl_jtag_state_failure 29.000s 4702.819us 19 20 95.00
lc_ctrl_jtag_prog_failure 10.000s 2378.096us 20 20 100.00
lc_ctrl_jtag_errors 38.000s 12139.397us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 7.000s 2435.152us 20 20 100.00
lc_ctrl_jtag_state_post_trans 8.000s 2776.439us 19 20 95.00
lc_ctrl_jtag_prog_failure 10.000s 2378.096us 20 20 100.00
lc_ctrl_jtag_errors 38.000s 12139.397us 20 20 100.00
lc_ctrl_jtag_access 10.000s 1693.114us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 4232.933us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 234.191us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.000s 72.949us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.000s 6091.820us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 1335.523us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 29.132us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 519.135us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 595.924us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 9.000s 3578.389us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 12.931us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 216.000s 169960.107us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 29.412us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 143.144us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 143.144us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 30.416us 1 1 100.00
lc_ctrl_csr_rw 2.000s 40.843us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 106.068us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 42.555us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 30.416us 1 1 100.00
lc_ctrl_csr_rw 2.000s 40.843us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 106.068us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 42.555us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 1184.132us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 1184.132us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1585.016us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 6.000s 1723.963us 20 20 100.00
lc_ctrl_sec_cm 4.000s 303.477us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.000s 9731.605us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 200.457us 20 20 100.00
lc_ctrl_jtag_state_post_trans 8.000s 2776.439us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 6.000s 4792.115us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 6.000s 4792.115us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 902.055us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 627.008us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 627.008us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 36.000s 16634.350us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 94104007405776164458171634659526192849347704348199070355277246666608592463501 1289
UVM_INFO @ 8275662207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112793766640150974877120472004231012703367759747493834670065804439333075556596 3403
UVM_INFO @ 5800959161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 371474369909642035399275365845650199109202246287187752455738924066994593193 166
UVM_INFO @ 6473771854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75928621995130102509408925159108917354388465781334613179243255930171689771127 1668
UVM_INFO @ 12220531167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 113565375622156494523318253006265888498568240080111081884735973137452105776033 175
UVM_INFO @ 58554904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 62252731125037461802594638218028161196707679228516015908541230478450499054317 176
UVM_INFO @ 303325559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 102018492553930106438799857377328512149328987395998607586522515981123037657219 778
UVM_INFO @ 116967489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---