Simulation Results: otbn

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.60 %
  • code
  • 87.06 %
  • assert
  • 96.73 %
  • func
  • 100.00 %
  • block
  • 99.34 %
  • line
  • 99.54 %
  • branch
  • 95.19 %
  • toggle
  • 85.92 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
96.32%
V2S
96.05%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 17.000s 1773.115us 1 1 100.00
single_binary 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 13.000s 34.992us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 8.000s 23.164us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 325.821us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 7.000s 21.448us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 142.289us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 8.000s 23.164us 5 5 100.00
otbn_csr_aliasing 7.000s 21.448us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 82.000s 12919.173us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 67.000s 4835.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 78.000s 910.463us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 94.000s 227.140us 1 1 100.00
back_to_back 8 10 80.00
otbn_multi 245.000s 1531.624us 8 10 80.00
stress_all 10 10 100.00
otbn_stress_all 121.000s 1209.904us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 37.000s 700.654us 58 60 96.67
zero_state_err_urnd 3 5 60.00
otbn_zero_state_err_urnd 10.000s 82.286us 3 5 60.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 23.000s 288.294us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 9.000s 68.105us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 7.000s 15.841us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 158.842us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 158.842us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 13.000s 34.992us 1 1 100.00
otbn_csr_rw 8.000s 23.164us 5 5 100.00
otbn_csr_aliasing 7.000s 21.448us 1 1 100.00
otbn_same_csr_outstanding 7.000s 30.551us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 13.000s 34.992us 1 1 100.00
otbn_csr_rw 8.000s 23.164us 5 5 100.00
otbn_csr_aliasing 7.000s 21.448us 1 1 100.00
otbn_same_csr_outstanding 7.000s 30.551us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 250.232us 10 10 100.00
otbn_dmem_err 46.000s 147.536us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 13.000s 129.566us 5 5 100.00
otbn_controller_ispr_rdata_err 15.000s 143.025us 4 5 80.00
otbn_mac_bignum_acc_err 14.000s 65.414us 5 5 100.00
otbn_urnd_err 10.000s 30.775us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 9.000s 100.474us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 10.000s 31.811us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 8.000s 71.056us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
otbn_tl_intg_err 65.000s 341.727us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 59.000s 857.898us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 1773.115us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 46.000s 147.536us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 250.232us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 65.000s 341.727us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 37.000s 700.654us 58 60 96.67
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 13.000s 250.232us 10 10 100.00
otbn_dmem_err 46.000s 147.536us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 82.286us 3 5 60.00
otbn_illegal_mem_acc 9.000s 100.474us 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 13.000s 250.232us 10 10 100.00
otbn_dmem_err 46.000s 147.536us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 82.286us 3 5 60.00
otbn_illegal_mem_acc 9.000s 100.474us 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 37.000s 700.654us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 13.000s 250.232us 10 10 100.00
otbn_dmem_err 46.000s 147.536us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 82.286us 3 5 60.00
otbn_illegal_mem_acc 9.000s 100.474us 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 11.000s 22.999us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 84.813us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 92.000s 821.835us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 92.000s 821.835us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 18.000s 64.428us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 27.000s 182.513us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
sec_cm_loop_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 22.000s 344.404us 3 5 60.00
sec_cm_call_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 22.000s 344.404us 3 5 60.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 25.000s 48.842us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_write_mem_integrity 8 10 80.00
otbn_multi 245.000s 1531.624us 8 10 80.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 19.000s 172.022us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 45.000s 128.180us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 530.000s 4203.536us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 436.000s 7178.787us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 11.000s 35.761us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otbn_stress_all_with_rand_reset 73049616556359890089857625358217128758491678177168536513554045531180488833623 279
UVM_INFO @ 2382838675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19832513840808677108859905912364006644546677115482823465980748095878718190267 248
UVM_INFO @ 4153178516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 25151905304817406194310853904675583442849363432411588921602447311371560245680 176
UVM_INFO @ 817359936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 58185492313486354044167580914869545209505442347573937511200096082685194323176 394
UVM_INFO @ 7178787021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 63406395949288433321743469107710901051552633908235848246523648730683257728798 157
UVM_INFO @ 124784216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 108127279232183507959090914318882934643343081957044237177118297275805042283576 392
UVM_INFO @ 5958862121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 4 test runs
otbn_rf_bignum_intg_err 107871218706276227572131158281755474790310553185703306283885514310539007700797 110
UVM_INFO @ 145583313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 42466445445388158816821410081566292336263766984423471322513542395782884015528 114
UVM_INFO @ 71056341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 77957723267382692795123568879707637642128573474337629549104662323430346387875 110
UVM_INFO @ 138249171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 72955315167129612359133240814170891015264881484499511511341752461500468225942 116
UVM_INFO @ 117962158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 4 test runs
otbn_stack_addr_integ_chk 27325968021227909024870252559595555737298920063254019518688340352953069915169 127
UVM_ERROR @ 17924376 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17924376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 21717456325561182201877226528483452110318145925012966365632671783489929968166 109
UVM_ERROR @ 82285814 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 82285814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 67175257072016396999479926986719943425249092308212956395097401922652183768572 113
UVM_ERROR @ 63183546 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 63183546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 109220734129291499207741154368681229810314713409565370852732699877922789692944 105
UVM_ERROR @ 27051960 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 27051960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_passthru_mem_tl_intg_err 88173303617969215625638103106233582762795246656965602863350344011371856598041 101
UVM_INFO @ 32120836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 8058912571652240620299859794544987406461966957480467701849948927892463315385 153
UVM_INFO @ 78810406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_multi 99518036365989787997178553926798291158213103471956388040649348327681017822314 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_escalate 31838306054435821729018621686511479712353976373772065032058624732914459936472 106
UVM_INFO @ 24941623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 73795091427634396089090822293008012946643155154530600065887791216268355479607 105
UVM_INFO @ 2822183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---