Simulation Results: rom_ctrl/32kb

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.60 %
  • code
  • 92.68 %
  • assert
  • 97.82 %
  • func
  • 99.29 %
  • block
  • 96.56 %
  • line
  • 97.24 %
  • branch
  • 93.55 %
  • toggle
  • 84.69 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.000s 405.684us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.000s 53.099us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.000s 53.523us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 178.317us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.028us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 140.151us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.000s 53.523us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.028us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.000s 54.335us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 73.920us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 165.717us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 12.000s 3595.755us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 5.000s 1354.068us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 57.084us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 210.946us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 210.946us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 53.099us 1 1 100.00
rom_ctrl_csr_rw 3.000s 53.523us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 150.987us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 53.099us 1 1 100.00
rom_ctrl_csr_rw 3.000s 53.523us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.028us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 150.987us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 3595.162us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
rom_ctrl_tl_intg_err 33.000s 925.975us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.000s 405.684us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.000s 405.684us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.000s 405.684us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 33.000s 925.975us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
rom_ctrl_kmac_err_chk 5.000s 1354.068us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 43.000s 15916.496us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 3595.162us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 128.000s 445.703us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 91.000s 23951.249us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 21607105175758084224736262582515165834851992029893257344195908277780228996989 90
UVM_INFO @ 172332952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 77319150175689898085027862242326120514073279790890539591120872898913656916956 92
UVM_INFO @ 337113676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 67403936060331335672521788795932808871714406052837335813237361144700844609851 90
UVM_INFO @ 196203611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 6159377521369607625413613172013805450990516608473967704523769689559357685099 88
UVM_INFO @ 165716967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 29998791381556574299570503121835799923112328723684656712379646478873355746105 88
UVM_INFO @ 1847097694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---