Simulation Results: rom_ctrl/64kb

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.35 %
  • code
  • 92.76 %
  • assert
  • 97.23 %
  • func
  • 99.05 %
  • block
  • 96.66 %
  • line
  • 97.24 %
  • branch
  • 93.82 %
  • toggle
  • 84.74 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.000s 1446.809us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 83.379us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 62.676us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 185.232us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 101.104us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 61.940us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 62.676us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 101.104us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 77.755us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 52.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 5.000s 1331.265us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 20.000s 1439.972us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.000s 716.383us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 4.000s 51.661us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 1345.055us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 1345.055us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 3.000s 83.379us 1 1 100.00
rom_ctrl_csr_rw 4.000s 62.676us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 101.104us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 138.972us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 3.000s 83.379us 1 1 100.00
rom_ctrl_csr_rw 4.000s 62.676us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 101.104us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 138.972us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.000s 2047.996us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
rom_ctrl_tl_intg_err 59.000s 213.282us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.000s 1446.809us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.000s 1446.809us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.000s 1446.809us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 59.000s 213.282us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
rom_ctrl_kmac_err_chk 10.000s 716.383us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 81.000s 29015.441us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.000s 2047.996us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 248.000s 1658.237us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 79.000s 5622.701us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 113170884190033407053847931225942277755054032777729759386210341447801835775093 94
UVM_INFO @ 623074868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 104026765892894155921869929515102391720826279172552802364308318587868730203298 92
UVM_INFO @ 7806114358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 33287112614104795195481738336416409226934635304951266950783683627315683996172 94
UVM_INFO @ 1741926428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 67216565066245266290974070692852773174375470205204658848071153228998139052819 88
UVM_INFO @ 1331265434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 79030145913649696694456373817782393045359087600757407100483692402115657976705 88
UVM_INFO @ 1360749065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---