Simulation Results

Simulation Results: rv_dm/use_dmi_interface

24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.52 %

code
83.53 %

assert
96.90 %

func
97.14 %

block
94.01 %

line
94.48 %

branch
83.79 %

toggle
75.51 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		46.11%
V2S		100.00%
V3		10.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	48.000s	975.712us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	48.000s	237.486us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	184.120us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	65.000s	20732.579us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	46.000s	205.306us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	75.000s	22852.529us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	54.000s	7972.151us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	105.000s	59724.605us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	137.000s	72320.303us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	42.000s	477.051us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	45.000s	426.096us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	42.000s	266.854us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	42.000s	215.602us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	49.000s	131.393us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	51.000s	685.506us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	40.000s	102.813us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	49.000s	563.426us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	42.000s	477.051us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	35.000s	311.341us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	45.000s	337.875us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	42.000s	266.854us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	46.000s	85.706us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	145.212us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	50.000s	48.112us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	95.000s	15775.569us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	71.000s	14094.488us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	44.000s	170.667us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	71.000s	14094.488us	1	1	100.00
	rv_dm_csr_rw	50.000s	48.112us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	33.000s	146.820us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	44.000s	25.382us	1	1	100.00

83/180 passed

46.11 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	48.000s	975.712us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	42.000s	308.307us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	44.000s	120.183us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	50.000s	169.597us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	51.000s	1036.322us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	60.000s	12523.983us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	114.578us	0	20	0.00
bad_sba				3	20	15.00
	rv_dm_bad_sba_tl_access	52.000s	6850.357us	3	20	15.00
sba_autoincrement				7	20	35.00
	rv_dm_autoincr_sba_tl_access	89.000s	31187.241us	7	20	35.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	48.000s	248.605us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	806.089us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	46.000s	353.232us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	47.000s	64.096us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	60.000s	9760.743us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	107.000s	3992.796us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	37.000s	256.339us	1	1	100.00
stress_all				0	20	0.00
	rv_dm_stress_all	10802.190s	0.000us	0	20	0.00
alert_test				10	10	100.00
	rv_dm_alert_test	49.000s	108.666us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	49.000s	485.978us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	49.000s	485.978us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	71.000s	14094.488us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	145.212us	1	1	100.00
	rv_dm_csr_rw	50.000s	48.112us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	2016.905us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	71.000s	14094.488us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	145.212us	1	1	100.00
	rv_dm_csr_rw	50.000s	48.112us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	2016.905us	5	5	100.00

V2S

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	53.000s	2461.584us	5	5	100.00
	rv_dm_tl_intg_err	58.000s	7372.948us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	58.000s	7372.948us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	806.089us	2	2	100.00
	rv_dm_debug_disabled	35.000s	54.773us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	806.089us	2	2	100.00
	rv_dm_debug_disabled	35.000s	54.773us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	48.000s	975.712us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				10	10	100.00
	rv_dm_buffered_enable	44.000s	223.213us	10	10	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	133.356us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	44.000s	133.356us	4	4	100.00
sec_cm_exec_ctrl_mubi				10	10	100.00
	rv_dm_buffered_enable	44.000s	223.213us	10	10	100.00

2/20 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	20	10.00
	rv_dm_stress_all_with_rand_reset	74.000s	2362.050us	2	20	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	347.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				36 test runs
	rv_dm_sba_tl_access	84177351987842246961227721683921115909227756084771891558214964652406346502403	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23831
	rv_dm_bad_sba_tl_access	6285846962140368950153743480291806819447945874961935935571449959343039958465	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23933
	rv_dm_sba_tl_access	77764883566811452618316764068495522987773079559440399368138718322720619769552	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23722
	rv_dm_sba_tl_access	6513621319683696214404896233145518150004469116594991312264941933253892712944	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23833
	rv_dm_sba_tl_access	111558568050510723777845753350296190158878966039570975919566701143111517996064	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_bad_sba_tl_access	36895706550763539627328035124639112810589046516923423718478552450354906477770	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10069
	rv_dm_sba_tl_access	18139008615678363930341439144710425610306460271658874034398171633358535122067	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23862
	rv_dm_sba_tl_access	24732309259972534180915637472810214377205487502384758771281402596214400667241	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	45680263430846865754407625683932139909878022659082939600903101475285207413857	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23754
	rv_dm_sba_tl_access	79512540207434187775358921342598749094732336595677071806896378125250087597284	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23858
	rv_dm_sba_tl_access	6533360983632617301644231413021957789141958067343271887118040372172536858571	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23813
	rv_dm_bad_sba_tl_access	56318136958593721320694178899863096043821285843137398051899993651910376011348	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23885
	rv_dm_sba_tl_access	87009129875091183202095740030420528027800496700674528663131029961526606390878	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	22133587906065722145544714624973525686883325069279095863769098646664291188547	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_sba_tl_access	82169593924898953824174705173885125065513928554641867835637834849671801310131	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23803
	rv_dm_sba_tl_access	38231926180654047468223828126058821544538097077802332734245123303576550135953	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_delayed_resp_sba_tl_access	56098496906949855241541056235072843079114861601795325838020540988417032815325	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23856
	rv_dm_sba_tl_access	870433056403103699794165619903318443342556171499751233329320799152143235911	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	64261449526150636947040982672469681467711227883987670661290237009529718748042	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23856
	rv_dm_autoincr_sba_tl_access	77622500433460476835559645985668321443267389974996517746771619059706929178727	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23771
	rv_dm_sba_tl_access	105193867594330247644694924442643711110118398549988790840944637374026247887761	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23811
	rv_dm_sba_tl_access	79759197622122593609118137096398496836039842195092476713013367471256943130076	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23729
	rv_dm_bad_sba_tl_access	102630755238386737675593815464288029061326712298088575467124936180818135524803	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_autoincr_sba_tl_access	24713298807543454563378709829496144038686901296521840637413081234806568845689	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24066
	rv_dm_sba_tl_access	29612501850594801542801526794112125786725569909049884433517131567840407198527	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	38749382010801413514160720406724824034815289361200512206982427365688419903072	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23985
	rv_dm_sba_tl_access	72960564138299807956479492116094301603684477597715853897761857703491732093336	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	112806937085022307310850766391167083235420442959640362461845879139166792294046	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23895
	rv_dm_bad_sba_tl_access	18624083677434556745494911137503891895293711623521558961423822301892107116946	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_sba_tl_access	106700248859856930022822381940111258657195869164346449800417724999125489747996	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_bad_sba_tl_access	105439216235315103954415339551422197512388605927241616092219625412870953223835	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23881
	rv_dm_autoincr_sba_tl_access	35456846094959693314056009502245957585789331617625519540311615397577333393648	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23854
	rv_dm_sba_tl_access	1680998600119756935182167044202806873851174844043837446649365577104621180387	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23844
	rv_dm_autoincr_sba_tl_access	3106362964948964305944700597400432385532394464719233291073417793452399005321	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23988
	rv_dm_sba_tl_access	106800682150542276255143473336480987288411081219864662555103799908716447815569	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23882
	rv_dm_bad_sba_tl_access	10790410120190857120899148554319344136765526024815263342875271343814045906812	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23734
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				34 test runs
	rv_dm_delayed_resp_sba_tl_access	15352863347922054002663759883001942582044121513539574814378276299777333984641	107	UVM_INFO @ 259636287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	100717772997512036189423333279019499331285885359312025252060357209716394062837	107	UVM_INFO @ 121131437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	112698789378976060383410586184201432707497387723675197092440259084317545581369	107	UVM_INFO @ 152030540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	112308541443325597229616394122693757924200949668038996805848195800918404180037	107	UVM_INFO @ 484283028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	70370562630180431566488507390927879549861186666837567620671995170720013670990	107	UVM_INFO @ 114578138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	3227630253558661377975234985765483926144194858799217038327308276705797557875	107	UVM_INFO @ 614746053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	71461860716436483899854331044039689406099852456885141363070190049273498289659	107	UVM_INFO @ 295757946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	18462031466706603688517346791772967544138432130214247737048524168573065459681	107	UVM_INFO @ 270060332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	33282321291482484823317770509506722551847760225375994869801511833371413001277	107	UVM_INFO @ 208524687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	50521150362983425389224652036516019061742260958488336485363595125569370338668	107	UVM_INFO @ 1071744554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	6632955922024219033017284207103805995857851337652317062311856858514976044356	107	UVM_INFO @ 233315131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89436412818199817266418208388753524887602823777118129645904240595611902582683	107	UVM_INFO @ 80256010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	33911224449062687359129546982468087175165770293170855092343526579738973047989	107	UVM_INFO @ 64336916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	24416807221593154133252613413074332956848244149063889205952284600949652240315	107	UVM_INFO @ 127165610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	18158988682059354269879951644625828591915632858919337723709985964607753048030	107	UVM_INFO @ 106091433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	92467366325857729898925116425152922148268134053259021961210609497120448179231	107	UVM_INFO @ 172064737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	12964493509218941399796684588292366007597668677681313552762851675983664187412	107	UVM_INFO @ 446652790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	112857174223871395182316083830270102059768424123293102264259233522021962071870	107	UVM_INFO @ 55759439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	30262652840793708369932099079804300357297024284023167226803473602198268093289	107	UVM_INFO @ 4851668594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2770207685306854056811719561336116532177620051964203671421938537666510550845	107	UVM_INFO @ 164719786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	29346628862970555371790418142486472173350593780176793250810983130463139782676	107	UVM_INFO @ 186745302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	19563987567155338570992160523361686714055490110551237804091017747795816143925	119	UVM_INFO @ 5192765525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	50415396863189176183659141875554786289635019377526186589319203263193879789490	107	UVM_INFO @ 146871524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	41434565090249640112076064889022326281709293772310469742458187324761552728631	107	UVM_INFO @ 122591995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35266128860013597955121666705399454965376943498544939487982487749540690949579	107	UVM_INFO @ 135317520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	60752532006307341835668148231140752649128149873514711935145302385533275070251	107	UVM_INFO @ 426855799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	82070300517128255379596173541678165410150337304420141756024938575783892496664	107	UVM_INFO @ 348104294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94549747126236588617395027596777563498663132379627719552173771411208884585983	107	UVM_INFO @ 297748335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	23368803553716459617495330261657996437290801114725778056306336035845393554958	125	UVM_INFO @ 17448450784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	46855956172800579651117645513269728997997779476811539135292175930933337278331	107	UVM_INFO @ 74002219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	39990741104096794664146486804704123203500846922675396114780271909076300176301	107	UVM_INFO @ 61793593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	8062579024035990388380393399721618267066605093457386812087041341042721770258	107	UVM_INFO @ 666011461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93730006747717273019697320935234484852576262792429893110671131399507376224888	107	UVM_INFO @ 467143840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	28977589587219018529824911728848305012407972055421742001136784697761179639133	107	UVM_INFO @ 40659982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				15 test runs
	rv_dm_hart_unavail	49826341055316030572955635438993299772786116699797660387520567253584386173908	87	UVM_INFO @ 266729291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	111072443323911119729365780515120799678319914992983514878657364541393377836766	87	UVM_INFO @ 64096470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	14782434088130962742210861509547318317427060197707652519358812692708274430781	87	UVM_INFO @ 73269722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	63333818409953769193900605567436872141607287677923964189316029410689513066622	87	UVM_INFO @ 317724505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	47584242116663511997529956304919730199961230629189758115882201078499197733391	87	UVM_INFO @ 284544528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	87797382900305616271937211228040656628666348329125063161483010746704401419304	91	UVM_INFO @ 121494352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	23103927588846991035495059483057259320983622747849116617960369056477837666752	92	UVM_INFO @ 185889321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66262255674134513658871795007367310478143598499562521679621137147896938152451	95	UVM_INFO @ 1728909804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35467500803277476217505546055116286355448201341698154768432261020847080953163	88	UVM_INFO @ 143257023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	17724089177784522563235403879456834628762596761830952768519939527378104080236	88	UVM_INFO @ 70421389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	67608600531193521693865760135524833004947274216955735039174406863684433008703	112	UVM_INFO @ 1346103860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96003170256828845169570400951354650284830714701042282920833370347429357919180	89	UVM_INFO @ 395190350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	27519789355907387334252036132509085582634468358243108981754947969469819266083	89	UVM_INFO @ 1517416436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	43315007927454170245715056489788757205938430015594167808327823644939964524853	106	UVM_INFO @ 390057130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	63796847074767921085381572727440384740439947948250033955968592920123713665048	99	UVM_INFO @ 939344330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				12 test runs
	rv_dm_mem_tl_access_resuming	104342099606809312650989938840419669788719313775738984621036735700022429564548	87	UVM_INFO @ 73625358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	105868242766138027971721868577595135503545389141424938424078675533400659459614	116	UVM_INFO @ 2206823153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	46517941226590861780005154573463472912476918961585762375179025837919254128764	87	UVM_INFO @ 215601828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	81996644963716638423391231845268708947003200549130705112243985222010193830270	89	UVM_INFO @ 302377512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78387482644295426979515120629333378067478890235281509383118270957304117344937	91	UVM_INFO @ 2633404276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	38787388965459212486581998956264839088071662099957618399901897976758120535698	88	UVM_INFO @ 233521379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72079078804547678459431842439147694068932882021961909652007118969341534581450	88	UVM_INFO @ 199421348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	41106927871946388098116477341022496119723821447243388035041009645443809248599	88	UVM_INFO @ 77873933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	835087660895195048050176020047126160676555449210549368473541804816403816235	109	UVM_INFO @ 883444120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	90164395593596737327840019729998897269185729056127060149069919420026797469445	92	UVM_INFO @ 1957135998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	85006466096115170787932632011534168630268592293266311496308867947354162184282	91	UVM_INFO @ 1564303461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	14602678683690160652444457983640440001527179250801637594023229360510505513076	125	UVM_INFO @ 2367565040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				11 test runs
	rv_dm_jtag_dmi_debug_disabled	16250927695212040517274634966040501328562515172875074823604299652947840310626	87	UVM_INFO @ 248605268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	56385929261166159185992999569060622209162411561804551607708041494341853079558	88	UVM_INFO @ 123786870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	108132369732592919197349709807246474018304358123386381504690240832383825721502	87	UVM_INFO @ 276212703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	28282268133984179566559915060115394419459729497575735544376212679034177225098	102	UVM_INFO @ 1104103162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	112448326193771591995789158186052475176770936759221372642071955807812322108300	88	UVM_INFO @ 133154483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	7151424272915424474624525177345259236884112321952710632222581222068458790375	88	UVM_INFO @ 389205093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	76469130491189811803005952221731544842660971865757363822976670511420292885365	118	UVM_INFO @ 1498068341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	16882052732325259033737664120077841523443384831939328314234570045396989401234	89	UVM_INFO @ 1347815252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	85922438747500015455807175835453297692084230079622053797122181270839364660028	93	UVM_INFO @ 352565299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97914019663422028763854813018482578466420246971332896610648909557668418186086	98	UVM_INFO @ 2392570107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98876038807055240377402112611826905726097758872397463936068518100378748542283	91	UVM_INFO @ 7501563227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				5 test runs
	rv_dm_stress_all_with_rand_reset	53917553744822333243475700092797166349482917529680139163419540280202644188520	97	UVM_INFO @ 3429220763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	81450269760492995769589646959198605122923971466960490294344842383094525038552	95	UVM_INFO @ 485686474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	3039414158046394207713890297945762093764903130451209631928004932771584745292	99	UVM_INFO @ 247586910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	13834945879603771426353340053038522975377829215479734470823146621364561953493	106	UVM_INFO @ 7635037840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80824522746562389001455343625271951102823629601198016002241497319387284392129	141	UVM_INFO @ 3477958812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	70731868129697889671458514092511055756721815513456068354109697236501206175136	None
	rv_dm_stress_all	18065199011347366828512734538908633135710684817157205021305949410422846972461	None
	rv_dm_stress_all	47486392691191440024290290938632988883445527323150860780953537546851394700055	None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	92611995504031278112661039279724402432714026854555252722358158865471881742285	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	18744925151358697903832816710513096509845102827918340228568441908994159366275	94	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---