Simulation Results: rv_timer

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.09 %
  • code
  • 95.85 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
47.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 698.018us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 45.320us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 12.629us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.000s 110.658us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 12.880us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 58.815us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 12.629us 5 5 100.00
rv_timer_csr_aliasing 2.000s 12.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 7.000s 1429.155us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1979.767us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 482.000s 422147.830us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 482.000s 422147.830us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 6.000s 6490.522us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 1.000s 13.612us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 41.711us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 42.695us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 42.695us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 45.320us 1 1 100.00
rv_timer_csr_rw 1.000s 12.629us 5 5 100.00
rv_timer_csr_aliasing 2.000s 12.880us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 445.202us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 45.320us 1 1 100.00
rv_timer_csr_rw 1.000s 12.629us 5 5 100.00
rv_timer_csr_aliasing 2.000s 12.880us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 445.202us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 33.337us 5 5 100.00
rv_timer_tl_intg_err 2.000s 130.825us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 130.825us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 5 10 50.00
rv_timer_min 13.000s 2043.439us 5 10 50.00
max_value 1 10 10.00
rv_timer_max 2.000s 49.641us 1 10 10.00
stress_all_with_rand_reset 13 20 65.00
rv_timer_stress_all_with_rand_reset 59.000s 8134.427us 13 20 65.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 23 test runs
rv_timer_min 3337151182928231801029113945671896732384994927849902114594231618848394182704 84
UVM_INFO @ 59140442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 35962644520961441691691948906116156261340035376704869931125128887729841695316 84
UVM_INFO @ 144427267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 92619169777115247162729778883010301861762870073636434161744496804695051901890 85
UVM_INFO @ 58957752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 61712975544735377628551062080413164475746540786149457241795215122783556405948 84
UVM_INFO @ 135895369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 80714497925918615374617395985606106309304954728679673181272572665711511922829 89
UVM_INFO @ 540104057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 41029429076145088667855926520898142278485517064109770383911710816214448125990 85
UVM_INFO @ 197827534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 108914765544188525733436585434110751034336263221557711424411950550029785866213 84
UVM_INFO @ 125216600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 100259596079241579042699376276118284993627323641433521983860485889632087787551 86
UVM_INFO @ 2043439132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 31295061733785880379561772546900115335412366347705188524706506910335204749365 84
UVM_INFO @ 827238328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 26861741812373696873605840953742990417541878154211784810718813513518594275950 84
UVM_INFO @ 687454957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 111628331030741949047753948465711687158979024166369863365318574933858499794762 84
UVM_INFO @ 59110275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 171967689954565084432645915830871556904096720903092949208050545480330009554 84
UVM_INFO @ 297099598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 25181056095770163888294323129238800651805986298459341674724746926732309782079 84
UVM_INFO @ 129510639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 84181076010626252482500670285832997366407496160666851204502029157498105865079 84
UVM_INFO @ 6632561469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 56213364042919714150979224014520090968077828970341621892555471745987007012512 84
UVM_INFO @ 515565848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 105600682092765602710031166499378066520932708606390981537976812086866192614801 85
UVM_INFO @ 407410349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 76481443722678997256090560020044956697037947526600080132620370088875405407538 86
UVM_INFO @ 742790064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 49622058807227671751850387682102929669130725548711989641423859113489726863952 85
UVM_INFO @ 333538591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 81259194968559952408039087617491050026881144369053720671539104053150965577529 85
UVM_INFO @ 184199578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 22004761974706023037689283454168124267614786901613187434846427661748962984488 84
UVM_INFO @ 1429154680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 10843826719331210190410265843975887111989315940124475308115948416227632588748 87
UVM_INFO @ 316660099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 39578384358013467024493939857802633083186988531624725933629412833295532763838 84
UVM_INFO @ 531345190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 72152472485313702218890672143271670708973479842688638438773613733539097775225 85
UVM_INFO @ 175342982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 93598719354187874334662371171630350666334285828351684494540228510649250402301 84
UVM_INFO @ 89745431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 18557943048433726314441384928007758704901921387944290741491497447342196107741 87
UVM_INFO @ 49641255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 81374925090828370686126576418637047392057489511409464410629375905439412864825 84
UVM_INFO @ 41960540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 103483757778150472046733973975520653667589219059255708491515316355611856500393 84
UVM_INFO @ 335589247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 72311718204422457516565277150808182614968085555843238146558015180845772561888 84
UVM_INFO @ 185941870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 105397041044540288455982084351716738025416397782285647135680935478347073916769 84
UVM_INFO @ 180680310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 15269637151724198146070887801774077161440373901504147610417872668093974116024 84
UVM_INFO @ 252629128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 35963308592043396603226733923120442834566132359274739809305118841276590656468 84
UVM_INFO @ 181058424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 74465179608326188755047013909284414700221621176966702962538352250633481375836 84
UVM_INFO @ 49248640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 6 test runs
rv_timer_stress_all_with_rand_reset 52599097187816021776430064634189958603066964251581908613297740131627414093546 102
UVM_INFO @ 79658063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 95005058597392189592046757140033017055250147559202634626864539803445873474587 228
UVM_INFO @ 6909642682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 111270170171655937065831385952796588250375972237599700576920389899719739896318 97
UVM_INFO @ 51963149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 15371839499308592145193175975838950762356654614836932874182973769839049601284 370
UVM_INFO @ 7343297551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 45716426141009629325862471450105970913321231049097750964017504578535580018181 332
UVM_INFO @ 2862245841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 8687951803625491884232723740422429750286534917186521642633928558971130780764 431
UVM_INFO @ 15868725311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
rv_timer_stress_all_with_rand_reset 93515097313530365995137859076658221148737947749242446434885690307257312547596 281
UVM_INFO @ 8192942651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---