Simulation Results: spi_host

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.88 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 50.000s 5869.019us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 29.442us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 44.955us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 312.023us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 17.429us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 37.854us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 44.955us 5 5 100.00
spi_host_csr_aliasing 1.000s 17.429us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 23.565us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 77.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 52.160us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 17.000s 1162.495us 10 10 100.00
spi_host_error_cmd 2.000s 23.451us 10 10 100.00
spi_host_event 428.000s 78273.561us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 695.371us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 695.371us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 695.371us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 443.000s 27900.095us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 64.000s 2033.659us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 68.065us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 695.371us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 695.371us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 50.000s 5869.019us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 50.000s 5869.019us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 43.000s 1453.716us 10 10 100.00
spien 10 10 100.00
spi_host_spien 19.000s 1791.292us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 131.000s 11219.830us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 855.272us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 17.000s 1162.495us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 17.599us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 20.254us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 230.067us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 230.067us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 29.442us 1 1 100.00
spi_host_csr_rw 2.000s 44.955us 5 5 100.00
spi_host_csr_aliasing 1.000s 17.429us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.825us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 29.442us 1 1 100.00
spi_host_csr_rw 2.000s 44.955us 5 5 100.00
spi_host_csr_aliasing 1.000s 17.429us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 18.825us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 2.000s 112.772us 25 25 100.00
spi_host_sec_cm 2.000s 70.971us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 2.000s 112.772us 25 25 100.00