Simulation Results: sram_ctrl/main

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.80 %
  • code
  • 95.85 %
  • assert
  • 97.96 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 1395.299us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 16.029us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 23.452us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 377.340us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 89.432us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 1415.239us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 23.452us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 89.432us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 310.000s 102901.325us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 146.000s 6461.608us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 44.000s 6736.961us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 251.000s 7761.053us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 222.000s 18049.525us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 65.000s 43075.042us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 58.000s 21260.512us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 67.000s 109918.106us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 4801.165us 8 8 100.00
sram_ctrl_partial_access_b2b 357.000s 22064.733us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 10.000s 9415.403us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 1313.890us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 934.322us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 15.000s 12952.769us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 1351.724us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 647.000s 22603.685us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 19.835us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 386.160us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 386.160us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 16.029us 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.452us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 89.432us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.326us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 16.029us 1 1 100.00
sram_ctrl_csr_rw 2.000s 23.452us 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 89.432us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.326us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 26962.616us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 768.083us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 768.083us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 12952.769us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 15.000s 12952.769us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 23.452us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 67.000s 109918.106us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 67.000s 109918.106us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 67.000s 109918.106us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 58.000s 21260.512us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 10.000s 9528.951us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 25.000s 26962.616us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 6.000s 673.888us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 1395.299us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 1395.299us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 67.000s 109918.106us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 58.000s 21260.512us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 1395.299us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 199.014us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 69.000s 4431.493us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 16589567154043221423305677153206618320042071449991426144829011811922883330836 86
UVM_INFO @ 1043531054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 109223600041644134372740434732505012729269766998505246768081488913351081835654 86
UVM_INFO @ 1313890392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 102183300165300142824013446519102266789882408286203220040430920150814739431920 86
UVM_INFO @ 2996958830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 11877717658667525814721612146967109398634617058011403135670795669911279632050 86
UVM_INFO @ 1379761359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 223323943413987165795852954716111577211136398527644011084445294591873329469 86
UVM_INFO @ 1082133719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 26978927429872414618800827120818973437325481029511486603969658016291873214557 86
UVM_INFO @ 2640860646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 115240978249445317085856006818129451394586302678570016367499853604537654417643 86
UVM_INFO @ 696906376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 38390183543063445797520495056391053033472176574440384914739805798128196241126 86
UVM_INFO @ 5490283714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 97518201242420340769692924366161284026928222933241596356686835868328781019422 86
UVM_INFO @ 8276199306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 23150440001971026047253763503758753175037510832980018333858060710484896391930 86
UVM_INFO @ 661099741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 19607410931587145417488372098601935197427676122445759701817193634161333084888 86
UVM_INFO @ 9415403367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 77938392739996949053433314984171087262683734841655164708856618792483199217197 86
UVM_INFO @ 2627911072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 24065792210913206122752659765094179994721336141896672471707108501621072564505 86
UVM_INFO @ 1378036610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 112049954524918743930712442212878966664064953715576637248583230403938531015969 86
UVM_INFO @ 1399754166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 82314933699271798792136673597177809342266485788642629622840637665080298354996 86
UVM_INFO @ 1392502177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 109778828130779295750754458328588038318444090323658667070196558017517578360048 86
UVM_INFO @ 2752576328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 39015031426774794687600726414652265973592903118189780681365829625268801966806 86
UVM_INFO @ 1330229912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 56079802553661957173830870239920412740216725583098899701610357860448087241850 86
UVM_INFO @ 934322108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 27783584089323276497376924561552440420890639583514112772690002346720790661844 86
UVM_INFO @ 691840899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104772566651926074250953787027922298640695284673907460631692787635606044567042 86
UVM_INFO @ 2656192078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 81807352779774826195456442841583872990677053091541252596095108263690864019540 86
UVM_INFO @ 663996200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 10853996997907356542282536422476692063380019646175811292413661338651188632338 86
UVM_INFO @ 685900273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 50368156479949881604907639583412122031768029365277225027911826924117184046986 86
UVM_INFO @ 2033834663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 62187593945514192968884679143730774969259965181072805162132758776664821125449 86
UVM_INFO @ 1372639970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---