Simulation Results: sram_ctrl/ret

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 82.51 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
98.86%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 45.484us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 23.513us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 19.668us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 876.239us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.045us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 38.167us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 19.668us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.045us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 14.000s 797.052us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 6.000s 194.062us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 16.000s 545.580us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 225.000s 14558.611us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 8.000s 598.114us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 24.000s 2500.143us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 9.000s 737.380us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 2684.736us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 72.565us 8 8 100.00
sram_ctrl_partial_access_b2b 448.000s 58927.691us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 98.951us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 26.940us 0 8 0.00
sram_ctrl_throughput_w_readback 3.000s 91.748us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2978.919us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 142.265us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 80.000s 11043.059us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 13.607us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 147.913us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 147.913us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 23.513us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.668us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.045us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 92.647us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 23.513us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.668us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 17.045us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 92.647us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 816.718us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 332.924us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 332.924us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2978.919us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 2978.919us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 19.668us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 2684.736us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 2684.736us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 2684.736us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 9.000s 737.380us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 7 8 87.50
sram_ctrl_mubi_enc_err 2.000s 113.608us 7 8 87.50
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 816.718us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 129.574us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 45.484us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 45.484us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 2684.736us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 9.000s 737.380us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 45.484us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 3.000s 445.633us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 29.000s 1100.697us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 60559515614967501815151641157497981174781508172812246560602436760483900684078 86
UVM_INFO @ 98950822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 62893328129490216923329826123037434844591040723738531159316759131254142181953 86
UVM_INFO @ 26940340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 185137030901360962042923960571166694085481236562698898345826321142727130406 86
UVM_INFO @ 103259751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 58285527715387166181772394168582737892992695404011938325158808610566850692043 86
UVM_INFO @ 112470448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62426450236750614628840965138399290351234844470489253388326436292822214575113 86
UVM_INFO @ 29149716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 45593641960354548000392727882519493982308712014155514580015732934878317678261 86
UVM_INFO @ 98621984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 25877546549040314386398054354422890591772483850115005149205094734170414497603 86
UVM_INFO @ 103151566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43047930896919281991571798377797830965927431989277605576403207341182409056971 86
UVM_INFO @ 60881444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 48843727003945609770538271544610691717354468788842692067971912398144324652281 86
UVM_INFO @ 55838958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 50846032701858594142105749107305560408116971451324147498882231738213327567375 86
UVM_INFO @ 29873511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 3464450772705624880051188872483571339564706438463366122414403512745805173385 86
UVM_INFO @ 35517683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 112883125175394223328698074524705618726579399242298055207944574471684951341622 86
UVM_INFO @ 22860104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 114755852018050203240421225621832447100535146203619084345873900213483459642227 86
UVM_INFO @ 115165870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 46353507366293179850554135771396812403603122506058546257484808472565863915017 86
UVM_INFO @ 30134729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 54447022725153170578560247464465891264628586019460119408308564742182802397351 86
UVM_INFO @ 124545936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 50118941333870114882477464933202914832326612673425370903621386133156745891039 86
UVM_INFO @ 351906575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 112572809166110285626584323121268108185295970612684307043710405918491392935423 86
UVM_INFO @ 28539980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 64083832348236774823795266851353380140210735269983974446862043823722720491658 86
UVM_INFO @ 91747782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 70163477917993260179466867312440557906817421056523054604110958147313765340361 86
UVM_INFO @ 119153665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30406082065137490514931940001770757368576657829128998864002633638044671809396 86
UVM_INFO @ 125903587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 80798068613572149672846615062047658075647917951737448802711062020496644446731 86
UVM_INFO @ 62128602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 51832097516544318210260089225038764205040246732291317248365299582612269325327 86
UVM_INFO @ 114926253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 73279426628946143704240206518765146267059707725441341278270518607442694548298 86
UVM_INFO @ 118693128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 6206481481114736290772080326757025178327033924718861600177772215586735088478 86
UVM_INFO @ 120987075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface sram_ctrl_prim_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
sram_ctrl_mubi_enc_err 66992798870247020284939626995391122143504647724441637843785512031756437180787 86
TL item was: req: (cip_tl_seq_item@13727) { a_addr: 'hd40cf080 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h74 a_opcode: 'h4 a_user: 'h24caa d_param: 'h0 d_source: 'h74 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 122749189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---