Simulation Results: uart

 
24/07/2026 15:00:35 DVSim: v1.49.0 sha: ffebaba json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.70 %
  • code
  • 92.73 %
  • assert
  • 97.69 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
95.65%
V2
97.48%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 18.000s 5843.149us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 39.804us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 2.000s 41.852us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 241.872us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 15.247us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
uart_csr_mem_rw_with_rand_reset 2.000s 10054.577us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 2.000s 41.852us 5 5 100.00
uart_csr_aliasing 1.000s 15.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 225.000s 123831.065us 10 10 100.00
parity 20 20 100.00
uart_smoke 18.000s 5843.149us 10 10 100.00
uart_tx_rx 225.000s 123831.065us 10 10 100.00
parity_error 20 20 100.00
uart_intr 472.000s 342626.376us 10 10 100.00
uart_rx_parity_err 158.000s 177544.813us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 225.000s 123831.065us 10 10 100.00
uart_intr 472.000s 342626.376us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 151.000s 267213.887us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 128.000s 94413.122us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 454.000s 178238.521us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 472.000s 342626.376us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 472.000s 342626.376us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 472.000s 342626.376us 10 10 100.00
perf 10 10 100.00
uart_perf 664.000s 26800.105us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 16.000s 9944.501us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 16.000s 9944.501us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 31.000s 47562.815us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 68.000s 50478.815us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 23.000s 6226.798us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 35.000s 5106.116us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 549.000s 104674.057us 10 10 100.00
stress_all 8 10 80.00
uart_stress_all 976.000s 243845.372us 8 10 80.00
alert_test 10 10 100.00
uart_alert_test 2.000s 14.900us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 2.000s 35.668us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 3.000s 247.441us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 3.000s 247.441us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 1.000s 39.804us 1 1 100.00
uart_csr_rw 2.000s 41.852us 5 5 100.00
uart_csr_aliasing 1.000s 15.247us 1 1 100.00
uart_same_csr_outstanding 2.000s 53.356us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 1.000s 39.804us 1 1 100.00
uart_csr_rw 2.000s 41.852us 5 5 100.00
uart_csr_aliasing 1.000s 15.247us 1 1 100.00
uart_same_csr_outstanding 2.000s 53.356us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 2.000s 58.244us 5 5 100.00
uart_tl_intg_err 2.000s 190.316us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 2.000s 190.316us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 56.000s 14934.631us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 6 test runs
uart_noise_filter 42315403517860075060529661701958298710238877599578476864745803887582108174446 83
UVM_ERROR @ 21225733 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 21745733 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 24225733 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 26425733 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 108187525725054563588636288069692706849662337006310474914415913988798930662835 89
UVM_ERROR @ 18796300683 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18801540683 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18809310683 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 18813200683 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 106408258153272376315175449542840134300085393686223855968760667209254527432036 83
UVM_ERROR @ 13914440 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 14945723 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 16924953 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 17904151 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 23367290065949740676005285798753350770925690437458933175364992950726354707943 89
UVM_ERROR @ 8061751779 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8062691779 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8063601779 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 8064511779 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 58011826256892219814999052915990187700657732526809698379525115075213115063353 84
UVM_ERROR @ 50690391126 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 50690613348 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 50691946680 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 142 [0x8e]) reg name: uart_reg_block.rdata
UVM_ERROR @ 50692168902 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 112695826542848919896442257256396326525208746763697389618087181621327131091853 93
UVM_ERROR @ 69042658804 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 69971207899 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 69971291233 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 69971332900 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (48 [0x30] vs 175 [0xaf]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 5 test runs
uart_noise_filter 596486746771228262906747730532953225881627821786224493216468225378671758334 84
UVM_ERROR @ 649351276 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 649517946 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 649732236 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0
UVM_ERROR @ 649779856 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all_with_rand_reset 49386982574459204108715650928382299560781444590753748107155771478139465705488 90
UVM_ERROR @ 305400549 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 305480549 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_INFO @ 583400549 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/766
UVM_ERROR @ 641640549 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
uart_noise_filter 85611718391342492312905719761649907016205442430653799054376483630220940901491 85
UVM_ERROR @ 6276956672 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6277047581 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (224 [0xe0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6359895983 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 6359895983 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 18302103779776095707161491418644506381383535147575248471683195849103752187219 93
UVM_ERROR @ 30721298764 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 30721543660 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 30721584476 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 30721727332 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 22944830245102585689232860055858866238450452989466371528898838406343848655753 92
UVM_ERROR @ 79777819603 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 79778111272 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (124 [0x7c] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 80322657295 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 80322740629 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_FATAL (cip_base_vseq.sv:465) [uart_common_vseq] wait timeout occurred! 1 test run
uart_csr_mem_rw_with_rand_reset 105277544698062703574123275275919870692554303153295573701605187080385098796005 89
UVM_INFO @ 10054576645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all_with_rand_reset 93439193650993167905778350014593720045266138738527969607461648953135029285995 117
UVM_ERROR @ 1319859933 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 1319859933 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 1364959933 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/815
UVM_INFO @ 1421639933 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/815