Simulation Results: ac_range_check

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.58 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
97.73%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 49.000s 6681.623us 19 20 95.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 71.000s 9463.863us 20 20 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 21.336us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 86.521us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 43.000s 30518.022us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 22.000s 5517.373us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 122.112us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 86.521us 5 5 100.00
ac_range_check_csr_aliasing 22.000s 5517.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 5.000s 250.171us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 32.000s 1994.438us 1 1 100.00
stress_all 8 10 80.00
ac_range_check_stress_all 213.000s 8168.449us 8 10 80.00
alert_test 10 10 100.00
ac_range_check_alert_test 29.000s 12.788us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 16.824us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 113.390us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 113.390us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 21.336us 1 1 100.00
ac_range_check_csr_rw 3.000s 86.521us 5 5 100.00
ac_range_check_csr_aliasing 22.000s 5517.373us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 660.469us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 21.336us 1 1 100.00
ac_range_check_csr_rw 3.000s 86.521us 5 5 100.00
ac_range_check_csr_aliasing 22.000s 5517.373us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 660.469us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1947.114us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1947.114us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1947.114us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 25.000s 1947.114us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 130.000s 10295.962us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 30.619us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 3651.895us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 411.000s 6695.180us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 52.000s 16059.546us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 2 test runs
ac_range_check_stress_all 74918337420829866964857983781466951948773338445963216791976706294404201396684 4643
UVM_INFO @ 2531416034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 64119440621010798354912353116862137103698971895098231758271915386642332262676 4634
UVM_INFO @ 1009519879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_predictor.sv:163) [predict] Unable to get any item from tl_filt_d_chan_fifo. 1 test run
ac_range_check_stress_all 9667766723420693418045780815073634199328169919673624558177313174025666239941 14307
UVM_INFO @ 100613830755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---