| V1 |
|
100.00% |
| V2 |
|
89.94% |
| V2S |
|
98.05% |
| V3 |
|
30.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.980s | 569.085us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 12.280s | 257.140us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 605.450s | 21696.538us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 148.860s | 1316.961us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 15.390s | 294.817us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 12.280s | 257.140us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 148.860s | 1316.961us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 371.900s | 31111.094us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 74.780s | 964.512us | 50 | 50 | 100.00 | |
| entropy | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2901.780s | 68113.076us | 24 | 25 | 96.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 66.600s | 1442.284us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 42.750s | 1099.656us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 97.670s | 1689.925us | 50 | 50 | 100.00 | |
| ping_timeout | 23 | 50 | 46.00 | |||
| alert_handler_ping_timeout | 476.510s | 47407.349us | 23 | 50 | 46.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 3600.128s | 0.000us | 47 | 50 | 94.00 | |
| alert_handler_lpg_stub_clk | 3453.440s | 80716.678us | 50 | 50 | 100.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 5000.290s | 195708.201us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 1 | 20 | 5.00 | |||
| alert_handler_entropy_stress | 29.980s | 1825.700us | 1 | 20 | 5.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 6.610s | 132.972us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.250s | 11.247us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 26.150s | 449.396us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 26.150s | 449.396us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.980s | 569.085us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.280s | 257.140us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 148.860s | 1316.961us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 42.210s | 1570.872us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 11.980s | 569.085us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 12.280s | 257.140us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 148.860s | 1316.961us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 42.210s | 1570.872us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 469.210s | 24171.064us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 469.210s | 24171.064us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 469.210s | 24171.064us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 469.210s | 24171.064us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1395.170s | 69250.322us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 100.120s | 4986.008us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 100.120s | 4986.008us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 469.210s | 24171.064us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.550s | 1553.945us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 66.600s | 1442.284us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 47 | 50 | 94.00 | |||
| alert_handler_lpg | 3600.128s | 0.000us | 47 | 50 | 94.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 66.600s | 1442.284us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2901.780s | 68113.076us | 24 | 25 | 96.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 2901.780s | 68113.076us | 24 | 25 | 96.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 39.400s | 1146.600us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 3 | 10 | 30.00 | |||
| alert_handler_stress_all_with_rand_reset | 156.770s | 15955.695us | 3 | 10 | 30.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 26 test runs | |||
| alert_handler_ping_timeout | 110380374487210727764107097473297137875778096785187277466884637981221285337162 | 110 |
UVM_INFO @ 5086223576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 35693777021137809654134410287513184436370751910026152847284456480813253571615 | 110 |
UVM_INFO @ 3248628523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 21330870836079152956136952718574277169682804808402601799405165797604041500540 | 116 |
UVM_INFO @ 6180855459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 81087739870875423750924753207731321166020236764006698802836660115257625435304 | 92 |
UVM_INFO @ 2061851111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45402223118586505573623053305838552841720079444098130854761332757532681295621 | 122 |
UVM_INFO @ 29344788518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 26072983966980005318119925723359134265906343192314903475051271844583919087590 | 127 |
UVM_INFO @ 9573812288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74200805180494490001762453584448234730465226897509803088318284254366198246230 | 105 |
UVM_INFO @ 9194253525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 57415297437184718137060478982652671092678155846226812258730646870785762804518 | 90 |
UVM_INFO @ 4219586397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 17608234799991378826050827898934764542042499743854614262699781561863470067611 | 156 |
UVM_INFO @ 47407348993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74427576527262530349222449432173255268336733586073490314706509046283207628018 | 87 |
UVM_INFO @ 1431477139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 37487418803131147341058078401094932591312730297983251098976787998379967770427 | 158 |
UVM_INFO @ 22426537085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 88910947430082139788033971370576687170547830048447990421110863072353927901651 | 104 |
UVM_INFO @ 70269956483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 86922593874965459784032768701045434207854795564751160022588969014624819313084 | 95 |
UVM_INFO @ 5282950525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 3729189997165791921021057604303833675045596146062316287441066943275544288749 | 117 |
UVM_INFO @ 31278887244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99293643445536218569623999796746339947019669078588126077404346135559219840815 | 89 |
UVM_INFO @ 11122756098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 28329050448797233537234733266010027075180584766823731795877060503502911054011 | 98 |
UVM_INFO @ 7356344292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99283405316932644151655379228095709123373276768711232548185036087533939233135 | 89 |
UVM_INFO @ 10664766808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 6837729745384245093514937729146366752755323958437504285834215257919553794433 | 124 |
UVM_INFO @ 43164539735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 15067008928580158284659878863790467290563622912109309416203928995083358881379 | 86 |
UVM_INFO @ 22192943611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 59375047295486558348636061654173887927561317795748196471515484447939438610271 | 98 |
UVM_INFO @ 7488421862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 25161926315497590262376244876551302579080489267762324826490068055374564162340 | 155 |
UVM_INFO @ 13222346321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 74111652442596347699081742228576972739888772179100760441786391380859631155918 | 155 |
UVM_INFO @ 45446334317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 52110215151226286185716019312911591691637649303924518611882483573059067982072 | 148 |
UVM_INFO @ 30762557664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 85166041957156201078355591379101927885410849667929964261915543010694893628692 | 132 |
UVM_INFO @ 9132122573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 54525729050174717676241241719254078558483342931121069124853516443386123662961 | 110 |
UVM_INFO @ 3962366393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 193917151314034671613094670698413355693356892622680858948150221898684965244 | 92 |
UVM_INFO @ 361749021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 19 test runs | |||
| alert_handler_entropy_stress | 72923102200168133466526122596999438074067725217357687820382005940979739252694 | 188 |
UVM_INFO @ 1357549724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 83817033428215247532154782882471471123530593945479662070805174129097791941611 | 160 |
UVM_INFO @ 254136482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 83911655349773254431658202159546644075439811592922857744465829351808479278465 | 177 |
UVM_INFO @ 112836222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 32088195642669108561183798898303863243693710959214475276807275112232014206989 | 165 |
UVM_INFO @ 1628926439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 43229767326384082315721406069354295416139785116050879686553598723132592864011 | 211 |
UVM_INFO @ 361661420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62993546542014924263226390980539455600128239007251158177817125584967726943352 | 227 |
UVM_INFO @ 7625894728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 94472703412182210141522867856987476078941151520299535614516869407107609692091 | 201 |
UVM_INFO @ 378950297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 80127224340670454062223847803409418791686498259626256162803997991576687466942 | 209 |
UVM_INFO @ 1100120377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 52970005640904934075419682457986279332688590727877652206522112641274338283505 | 207 |
UVM_INFO @ 557881036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 74889644392024402945715068218259300023767641877287403806985295110110312969142 | 126 |
UVM_INFO @ 184812286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 25508052294914873298455060740622242255108273922110266547519615440801810033384 | 224 |
UVM_INFO @ 177729316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 30533097525114067373627768180297887404450008893991440164169428319678431427271 | 174 |
UVM_INFO @ 282006174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 8334066374789329171612423227096994325767763355208861667694762410627461927564 | 174 |
UVM_INFO @ 1272755505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 21934740026250068882734963435495932044915677854182490379136574517373202520268 | 136 |
UVM_INFO @ 524942134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47564924201037189336634396907672151523572999522067292133741498423447648695090 | 216 |
UVM_INFO @ 2927935593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 5191557065424772351995430174224099060298268666684273687852825644002709378693 | 190 |
UVM_INFO @ 451311341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111786156610460251228026034727260143613567379153222167590000269732669810896034 | 212 |
UVM_INFO @ 1825699536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 55410897394317866766078128672686223579863987738880697445804909757354568915103 | 201 |
UVM_INFO @ 131839555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68206003793095640461759345779611200337835755372556155783016207383249945590784 | 171 |
UVM_INFO @ 111468131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 7 test runs | |||
| alert_handler_stress_all_with_rand_reset | 4420982827895497022517749392632958957061790117976148254082605675077782801052 | 83 |
UVM_INFO @ 2353722726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 41908013813460493938991728514994288134870202033433934383348123571534699083452 | 134 |
UVM_INFO @ 4256819727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 7206305549982442040057749657870858818897416086430556258060114639189343104515 | 137 |
UVM_INFO @ 6877233555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 72851159900119483292037051838595023206511349278666769891575761853244179601530 | 123 |
UVM_INFO @ 6788137939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 41433810790481694109069119260429919615153731575970291907469549617861446216321 | 182 |
UVM_INFO @ 15955694989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 25252937995051367671336382475891699406568605151659438525610713584856204088599 | 131 |
UVM_INFO @ 1363304438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 89309307565194931423036031706868155741945782922400912736500484492389626783247 | 109 |
UVM_INFO @ 7894589358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 2 test runs | |||
| alert_handler_ping_timeout | 110451763548087439613927688376231559372869728121458672330947818851942666227917 | 85 |
UVM_INFO @ 1008089769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 47059585848145177554098977981964086812092951451119638862342951138646238284197 | 85 |
UVM_INFO @ 108729889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt | 1 test run | |||
| alert_handler_entropy | 58987874111701070906942101705208638090866934160226481298240771162752481460919 | 85 |
UVM_INFO @ 1660087627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 80647239245707640947360365273451786252799020990179821447735267823424643658740 | 98 |
UVM_INFO @ 55494524120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_lpg | 59933544910610805964017116909028877625490572160976812807416931982471365601202 | 86 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| Job timed out after * minutes | 1 test run | |||
| alert_handler_lpg | 42951919997378537707948822648811653421557093353922258682202488199108706286716 | None | ||