Simulation Results

Simulation Results: clkmgr

31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
82.19 %

code
76.62 %

assert
93.80 %

func
76.15 %

line
90.27 %

branch
93.32 %

cond
87.02 %

toggle
100.00 %

FSM
12.50 %

Validation stages

V1		69.57%
V2		65.81%
V2S		24.76%
V3		5.00%

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	4.910s	268.632us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.850s	73.969us	1	1	100.00
csr_rw				1	5	20.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	2.610s	78.514us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.100s	6.849us	0	1	0.00
csr_mem_rw_with_rand_reset				4	5	80.00
	clkmgr_csr_mem_rw_with_rand_reset	2.580s	81.216us	4	5	80.00
regwen_csr_and_corresponding_lockable_csr				1	6	16.67
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
	clkmgr_csr_aliasing	1.100s	6.849us	0	1	0.00

77/117 passed

65.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.670s	50.190us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	4.130s	333.705us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.480s	44.229us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	4.910s	268.632us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.500s	43.077us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.300s	28.907us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.500s	43.077us	0	10	0.00
stress_all				0	10	0.00
	clkmgr_stress_all	6.220s	317.637us	0	10	0.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.740s	58.226us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	8.520s	394.405us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	8.520s	394.405us	25	25	100.00
tl_d_outstanding_access				2	12	16.67
	clkmgr_csr_hw_reset	1.850s	73.969us	1	1	100.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
	clkmgr_csr_aliasing	1.100s	6.849us	0	1	0.00
	clkmgr_same_csr_outstanding	1.570s	35.226us	0	5	0.00
tl_d_partial_access				2	12	16.67
	clkmgr_csr_hw_reset	1.850s	73.969us	1	1	100.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
	clkmgr_csr_aliasing	1.100s	6.849us	0	1	0.00
	clkmgr_same_csr_outstanding	1.570s	35.226us	0	5	0.00

V2S

26/105 passed

24.76 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				1	30	3.33
	clkmgr_sec_cm	123.680s	10044.073us	1	5	20.00
	clkmgr_tl_intg_err	2.250s	79.547us	0	25	0.00
shadow_reg_update_error				14	20	70.00
	clkmgr_shadow_reg_errors	2192.970s	200000.000us	14	20	70.00
shadow_reg_read_clear_staged_value				14	20	70.00
	clkmgr_shadow_reg_errors	2192.970s	200000.000us	14	20	70.00
shadow_reg_storage_error				14	20	70.00
	clkmgr_shadow_reg_errors	2192.970s	200000.000us	14	20	70.00
shadowed_reset_glitch				14	20	70.00
	clkmgr_shadow_reg_errors	2192.970s	200000.000us	14	20	70.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.870s	50.126us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.250s	79.547us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.500s	43.077us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.300s	28.907us	0	10	0.00
sec_cm_meas_config_shadow				14	20	70.00
	clkmgr_shadow_reg_errors	2192.970s	200000.000us	14	20	70.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.650s	165.914us	10	10	100.00
sec_cm_jitter_config_mubi				1	5	20.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
sec_cm_idle_ctr_redun				1	5	20.00
	clkmgr_sec_cm	123.680s	10044.073us	1	5	20.00
sec_cm_meas_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
sec_cm_clk_ctrl_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.230s	22.539us	1	5	20.00
prim_count_check				1	5	20.00
	clkmgr_sec_cm	123.680s	10044.073us	1	5	20.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				1	10	10.00
	clkmgr_regwen	1.300s	25.993us	1	10	10.00
stress_all_with_rand_reset				0	10	0.00
	clkmgr_stress_all_with_rand_reset	5.400s	263.280us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				26 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	8835580400356023843662317455390369117183707008667830677736617789708875321391	75	UVM_INFO @ 21809198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	8977649026179549009845876288591285973127774730437803728425852865671386210738	93	UVM_INFO @ 13986126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78427724115894578171267216961307204102712499986928977130420854602417111792197	101	UVM_INFO @ 23057753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48495688795396317886962363607173233576191168445195006297139271285880741157944	75	UVM_INFO @ 6627993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84761308833525643331022526290825944765878490606047088033760800485489657425277	82	UVM_INFO @ 6926153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	41582942822179538715789560246285124186438880152221240868155997815668815183338	75	UVM_INFO @ 3037432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	87314415058150154577368575333979893076258044192341635184482960792037737085131	75	UVM_INFO @ 13305619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	37113633442512737679214221508513945284947005189074804521630459367131343273850	105	UVM_INFO @ 20749255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	69172891609531894182446294293040958302202537685454542438469846417968553730436	75	UVM_INFO @ 4763188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	93798570359896241170130268673448507780714569248776118020087406255522118195581	75	UVM_INFO @ 12613177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	111621200853131825165715139722511071131083513594758568330498757316810644188721	89	UVM_INFO @ 15139174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64138944796189048947918879012920591790789636355729103509640470219699509557034	75	UVM_INFO @ 19938321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	16046738285708283815580575090609271479954536985503999530710991677961580792368	75	UVM_INFO @ 2974112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16805045891081554961182107161579735075159160817955443993676103654739011511069	75	UVM_INFO @ 15804629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12392052757011141552310417257396126321437071094911691128736574781339373807597	75	UVM_INFO @ 5879104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	101757967898622577818522079849761139374925695484360393820882706758423782327049	75	UVM_INFO @ 3577191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	112372075792632232008877230190341223561212900112878408786308665802707511240389	78	UVM_INFO @ 1659394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	61622642907227757671711975134998195825494353972396565946211806570617812159224	75	UVM_INFO @ 11634064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	16765127928942384648817861021108182676407851978515572675591414895892479031813	86	UVM_INFO @ 11697220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51170514601020569289641885404739493554574220913109346579411826262513476618125	111	UVM_INFO @ 16839570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	62594045554580609862681138687411585081492316860054649223307505336317033831203	75	UVM_INFO @ 3223439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	55188442817800743344126003438071007384510420125299507880831186162610790467545	83	UVM_INFO @ 6787777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51423756719227983466885937022110912093727713312710570739246696286470362936280	78	UVM_INFO @ 5836219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	23515128388595977760664355792154726301674193048851419790196030589768503011878	86	UVM_INFO @ 26866559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	110998222877877503700969184646785729358899929704780649549704526297572513163678	97	UVM_INFO @ 42091676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	102294461622850443679546388426704247131217017287564053437025991462367481644381	89	UVM_INFO @ 13043821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				25 test runs
	clkmgr_csr_rw	68743995899429338943307582498389149669825181075846026485883657199481292344386	75	UVM_INFO @ 2774971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	73939338835198742621478438846003743599167764295004677428970341892555573046017	75	UVM_INFO @ 6849109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	69136877653379943204022690459831019819818848707801482091958129542990425940058	75	UVM_INFO @ 7427537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	49410349615210037227059995906553351478338902717970053066830246662381920647735	76	UVM_INFO @ 7727103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	75799542490510046267878086611593846382907862650891239779206254457277509655985	75	UVM_INFO @ 9372785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10246773924951834555563778180010729241761427079434927932160017160158755427788	97	UVM_INFO @ 37179635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	13945530588682201803196679148390630475551905364683703838658647223635523298436	75	UVM_INFO @ 12974106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	27193779546616696287740549210995360199635103473756677512807054532781283519206	75	UVM_INFO @ 6323868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24551905878556287124871059830828235475882149731091909058428942839584269034593	86	UVM_INFO @ 8265772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	66393438703238234554008569588811880160753019069158104173888351426651045839610	93	UVM_INFO @ 15802577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115483827927984065505284118178975749906286445792341347986660438758085116193082	85	UVM_INFO @ 3778255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	32260085789105810446123523273060188805999499969655457903064923574455398281321	75	UVM_INFO @ 4715301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	11591151991778745231032714404951501989897299192410744815468253078315233720521	116	UVM_INFO @ 79547277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	7711469073127444736043723336322140660753011509747683741170882735739909404623	75	UVM_INFO @ 32902788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13819144964637658629958725701823803997491439811135075464238589981430614409779	82	UVM_INFO @ 6198301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	61580152924986208872715439037987482910178135054565426998089896813643191535055	85	UVM_INFO @ 10575646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	65488502064548700233015792052466484756735253520618717393669819272280856069157	75	UVM_INFO @ 3468813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	94434787107189967626195345861468362116264446764224013174751384873851716373858	86	UVM_INFO @ 6613197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110803227067648251339061738362529268428075144927707728102698818250027616206071	75	UVM_INFO @ 3482326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	112905644119709907341498877414850436079472267777015764491423341929156154803691	75	UVM_INFO @ 4082967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	55401328611852718393980545121951461360161909856812626770052781997230796327099	75	UVM_INFO @ 50126146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24109842105022834298332802036858964171328905117311812014657735432205510996397	97	UVM_INFO @ 22577850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77176507469040641475496052310964958175537463184333763180042091694923148040981	82	UVM_INFO @ 4435717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3392169879833183940726007067627599285431008931377101304981815919532678842196	75	UVM_INFO @ 11393806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	69115308884952358444736395555769175063834232551014602718802112128897760572716	75	UVM_INFO @ 1863631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				22 test runs
	clkmgr_frequency	26737731225268597394549267078039453429324790849920757955276506393877135067158	76	UVM_INFO @ 5812790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	62773918335920963745812997406613255208532377084335502107752349835193901619692	76	UVM_INFO @ 16325226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	4017840099893145315486960813585548257002581299776831659682063482417126672174	76	UVM_INFO @ 6822625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	35264639572394523553529118554099541354559166540062981669268691195089898184033	77	UVM_INFO @ 25088977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	11274942755112828714202922500442601803442669353143962665626084913198893742566	75	UVM_INFO @ 3909857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	19149260598801435099973642848833439873453735897059695252020348330897678690742	76	UVM_INFO @ 3805944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	50637871887200660464644014711679826182336304943837000013459087217079790237702	80	UVM_INFO @ 54220795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	87678478871574751316241769719536386680927242124613207577234685740315708801867	76	UVM_INFO @ 5504276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	97017891949330528278106466950216235746402879516649076148767893049303276474373	76	UVM_INFO @ 8336481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	22738824344651355598664115783684411890394398915005645471443955801417275668871	80	UVM_INFO @ 263280332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	86719759758599883262760432864542452316712579155593101095195984381155576524076	154	UVM_INFO @ 317637068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	37133410628243363147077526830953133821824368771409768696993529863063247347279	75	UVM_INFO @ 20594553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	81097221433822126412660363176898331616198618588707121864113251407934821604315	78	UVM_INFO @ 6378868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	40412097779468042097328720895685833449146012723006330657010619387603383765034	75	UVM_INFO @ 43077438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	101727283199338249225314385901895155999963575985403776009592612569330676306156	80	UVM_INFO @ 12721287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	92227280310686970543461707511302738837445010468153426524412109371527157581091	75	UVM_INFO @ 18276926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	89283686285711297084985627660811644383619890482515995075134049850857981843300	75	UVM_INFO @ 9122171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	86474702978638508812073572200870540010392858501265627267111525324073714678204	78	UVM_INFO @ 48680494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	113775041879259708627610384763081751990357436311644815115624280648158370770457	76	UVM_INFO @ 21717506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	2830367767493567534287164504493527600123605365793790011658847055160412678162	75	UVM_INFO @ 7551321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	61616124443920235437862228247671011675361842506373595487221604734682510113535	75	UVM_INFO @ 22273052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	38502319733749871343439977510424813683156869652068633815045488648157989401785	87	UVM_INFO @ 84094903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				18 test runs
	clkmgr_frequency_timeout	35621081653065953962646651052215347284049503068041572563241368976812211767477	78	UVM_INFO @ 3155032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	110494997995075439766397083869667599129517481291599114611494519991651052493663	79	UVM_INFO @ 3106403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	111832781238003852008977177329416407471175794189003989406769316412670801028347	77	UVM_INFO @ 6316383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	72759468599389525698824161580026861030853481333783801720355312341316283492727	78	UVM_INFO @ 28907069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	112565603864299836494435062491933629224215436418518621295268384012742110258373	78	UVM_INFO @ 9986031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	39483651048828380516688334688850734684686008500242714512890481382120991355684	78	UVM_INFO @ 7010326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	62404022512274404664998158499350966097066660777189906919916951570806924224793	79	UVM_INFO @ 19334336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	9451525507916190615915988270570728011880986284629599653893640018357872343213	78	UVM_INFO @ 5996220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	115444215366314340156936876034791373575968095549138310417267072011773315011126	78	UVM_INFO @ 3022331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	41343867875520560796281936340456863874910593337422756750278168250596796066926	78	UVM_INFO @ 4180565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	4935865310455088393549332965257689929102003208744435980044808704599847658454	113	UVM_INFO @ 345299812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	12665080533597583466756525551581319904994185318278078168538452196658796304374	77	UVM_INFO @ 3252314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	20691834227210456636486746078976592534344657119847683554765806679419579350944	78	UVM_INFO @ 7215610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	109110087912723359577584574303949159299166247415136981645254208075683431133143	77	UVM_INFO @ 5315544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	10309990213419232641996564788283690731604319821206606118764615496252387975987	78	UVM_INFO @ 3374900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	106429225363674725280830926688319368040077852177253904611008652627119211821111	79	UVM_INFO @ 37525319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	20846790689229361072451962961338311273907705652416848516799324454773734966666	78	UVM_INFO @ 4464103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	25532780247073262274439232712647790241086564588380506087492547773485277635954	79	UVM_INFO @ 15787084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	clkmgr_shadow_reg_errors	107471802862835643015687217865662496662973960941666654086332978732182765192894	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	76633311582519996837984630572110917690997577041659207891038391469740192013029	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	108043851918265761018625674666748614674401906208262591921535688403537485908787	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	88164293220416598040688345176112872512518507893008438524735804607711167094746	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	78543092660407321449728296167761445533253510066861707903120650020274795368471	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	87285634285170432954098051707146899873959865557439953060537985018421054856993	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	37670748679892222244554201182710464332011533956938578221599869417677784725770	75	UVM_INFO @ 5940558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	74635831595321583936821311921134445645671317699128853880504109985752213213225	75	UVM_INFO @ 35226121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	83521246304603941828392248943577157058396720305565290182411394395103301635795	75	UVM_INFO @ 12256669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	103179045898374212880814686383664153619489657386946102030991999445071145997165	75	UVM_INFO @ 3150513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	46772310737947091396029383154096700476202003802254352810033140245069705477322	75	UVM_INFO @ 3645661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				5 test runs
	clkmgr_regwen	69504606955893673619566398784362013722495172111778162208003985993017320490527	74	UVM_INFO @ 9902667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	108942903432043746668542355084605133843690738201516252502526578468423518455725	74	UVM_INFO @ 5170349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	51054343301349293233942885667752223558257051122648583290819683820240774004445	74	UVM_INFO @ 11820574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	77896409512528496924692467126498692577625457006523381403444828427691935434148	74	UVM_INFO @ 14681541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	50089595864734947687629124454268310196689994559321842428130302869815173398832	74	UVM_INFO @ 6145636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				4 test runs
	clkmgr_regwen	54528418588391839852021863340266770393386247574016042604766525980707762068733	74	UVM_INFO @ 2840055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	87974762204607613396691889234892422545963224470078635579056368624369570888503	74	UVM_INFO @ 2475523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	37043053707620726876717905161887793050755141873002618147688134109610520680497	74	UVM_INFO @ 1851235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	77768021578544606940098038780566954740152824972942450847893099861514853062983	74	UVM_INFO @ 9917623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				2 test runs
	clkmgr_sec_cm	78967109027049685673105230443480067211937990387149735103031011424952234065253	83	UVM_INFO @ 10044073239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	77278937091745108563725224592321484792744948732237992851830127495158785997356	291	UVM_INFO @ 10489709656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	33053857036750250140647999272661030765524842213269624623524990320279721225931	211	UVM_INFO @ 194067327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	79720348504605636206259931503051883718711472207661111649638368435519804060417	163	UVM_INFO @ 87497181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	94143095357296623038732612777976239892126401713655335875894479879755753989327	75	UVM_INFO @ 78514354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---