Simulation Results

Simulation Results: csrng

31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.78 %

code
96.20 %

assert
97.16 %

func
90.97 %

block
98.53 %

line
99.54 %

branch
96.38 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.09%
V2S		99.22%
V3		10.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	5.000s	127.370us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	30.000s	22.218us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	30.000s	20.001us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	45.000s	565.335us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	33.000s	188.232us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	31.000s	93.413us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	30.000s	20.001us	5	5	100.00
	csrng_csr_aliasing	33.000s	188.232us	1	1	100.00

1282/1307 passed

98.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	73.000s	7158.527us	500	500	100.00
err				500	500	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
cmds				1	25	4.00
	csrng_cmds	208.000s	17434.303us	1	25	4.00
life cycle				1	25	4.00
	csrng_cmds	208.000s	17434.303us	1	25	4.00
stress_all				24	25	96.00
	csrng_stress_all	665.000s	30392.236us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	3.000s	97.177us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	30.000s	38.542us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	13.000s	694.202us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	13.000s	694.202us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	22.218us	1	1	100.00
	csrng_csr_rw	30.000s	20.001us	5	5	100.00
	csrng_csr_aliasing	33.000s	188.232us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	161.862us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	30.000s	22.218us	1	1	100.00
	csrng_csr_rw	30.000s	20.001us	5	5	100.00
	csrng_csr_aliasing	33.000s	188.232us	1	1	100.00
	csrng_same_csr_outstanding	5.000s	161.862us	5	5	100.00

V2S

1275/1285 passed

99.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
	csrng_tl_intg_err	25.000s	1595.376us	25	25	100.00
sec_cm_config_regwen				21	30	70.00
	csrng_regwen	3.000s	75.399us	16	25	64.00
	csrng_csr_rw	30.000s	20.001us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	73.000s	7158.527us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	665.000s	30392.236us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	73.000s	7158.527us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	665.000s	30392.236us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	73.000s	7158.527us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	25.000s	1595.376us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00
	csrng_sec_cm	7.000s	461.289us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	22.000s	1463.535us	200	200	100.00
	csrng_err	30.000s	26.544us	500	500	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	84599476606771772345605516000855612169564774937253261999289675668755682520073	100	UVM_INFO @ 60344302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45329710815183214354383323190867987762346171727502123806400765279025593411753	100	UVM_INFO @ 164319620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79057509505761954267259431797436315727697055941554246119133356506262058114770	100	UVM_INFO @ 241996979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	5214763328394568049966591101025235532175545324897568389973042486927445799909	100	UVM_INFO @ 22892830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	72361655069148131021126390833300375460760733580727509764004216682959344181162	100	UVM_INFO @ 45090936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	15489461212620532900082883285306741749268681425898027855283020957965429610211	100	UVM_INFO @ 127551608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	102967411182015281837742677293821044949829881683688435125398695333847954455971	100	UVM_INFO @ 227804713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	104691806500772771877704142414862201243439430362478399116002162491891762095885	100	UVM_INFO @ 417152525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	334603301039192490602708430137722604726110405512533724172204354407185826848	100	UVM_INFO @ 39113375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	21558715989727293513386750392404775771667810462838378569944296226105457408722	100	UVM_INFO @ 50087363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38514861075979413236284595476106251759314726076629447223690079716131229265164	100	UVM_INFO @ 237809455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40487439663330511166082554721669833867410290208642616204484872832231619240234	100	UVM_INFO @ 270267203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	42723507805958582489547080888635709777327750723144812510017489821749194346580	100	UVM_INFO @ 254983309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6018667414183710154337240430136683185647046879743104019674380057862542517729	110	UVM_INFO @ 103116061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47140283053915783039634783930813347534962117442170057779945371602204162326424	100	UVM_INFO @ 98424618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94774483100915795676662604899392535253970183274685732798960263269912754046551	100	UVM_INFO @ 23032415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107780473155006111172119909141974053865162190854523775277244128667719907109269	100	UVM_INFO @ 26667737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33760487094243113424865580624776265797471014804203054558689102511415881264662	100	UVM_INFO @ 54409721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	50891011930037408429511293530256216743092027792566858120884266989481979723807	110	UVM_INFO @ 341674931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70531724061064712063370423257247034592945619581092976651698359892029382396482	100	UVM_INFO @ 153530709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79894987773803890679224230653984034567722946923535030588051162982453886780174	100	UVM_INFO @ 24352257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				7 test runs
	csrng_regwen	75170735063008450901497208352995135685025380605762714623769814868212492573349	99	UVM_INFO @ 2619385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	24839802741435500338586296200175132178509642640487564761423258028778501397353	99	UVM_INFO @ 1789029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	79653918089408718241344569091600753999777605017340926063077417496394438145549	99	UVM_INFO @ 5912443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	29128029219394146001948508804791679165852149159976228685738935467442716063584	99	UVM_INFO @ 2814397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	39949845030250111399804453672044598495623520379161445077279812426454460005986	99	UVM_INFO @ 1248966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	58847122070189593880703830758359451700107439517858111770006905007610537013897	99	UVM_INFO @ 4467550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	78527073966132443475487615316543461485549599598216700481346036976887126003448	99	UVM_INFO @ 5277632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	csrng_stress_all_with_rand_reset	2495609004909985791923911537347070352543056260704337429226267131529350455390	None
	csrng_stress_all_with_rand_reset	60576953345057354138958345933017796900769710099443706811401694749439398162261	None
	csrng_stress_all_with_rand_reset	115063894184363332714817649592495286500957791197448030593722405723367508835468	None
	csrng_stress_all_with_rand_reset	92003564805295935097753569018794961304638805479026599353334159126131223916585	None
	csrng_stress_all_with_rand_reset	79876669121276116252919252731434152398129319764348040853325554253702142586948	None
	csrng_stress_all_with_rand_reset	61128816347253598084296463209251540534348653071459564301589155567461528307292	None
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	10698844645373909298471824547252997705832395591888556877413612229089675224335	103	UVM_INFO @ 100606937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68067716915575300278472479520722668906935254086268143579700584870160439135792	103	UVM_INFO @ 671549253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				2 test runs
	csrng_stress_all_with_rand_reset	14502515545427272797458827577791941390471488626171959401013002273385709093421	114	UVM_INFO @ 24359825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	25517768819754993591873446665888229863378266518609718031188998994553480507651	135	UVM_INFO @ 2475633511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				2 test runs
	csrng_regwen	2952864306712835780557181756547444398625487883559633950551048751672754892717	99	UVM_INFO @ 3761189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	41266043093294296241103778392253897355183965728345659282838863312601968948679	99	UVM_INFO @ 6605146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	60300973527585548775107658475945526967067728145393602207535672214849303758925	104	UVM_INFO @ 1698704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	30121514928235110186740177850840807871377351640230830734917094020164839759002	104	UVM_INFO @ 102805581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	107879033077558338987352792362185745430504349163768333997677373775290662882732	108	UVM_INFO @ 22961088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---