Simulation Results: edn/edn0

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.13 %
  • code
  • 95.28 %
  • assert
  • 98.23 %
  • func
  • 58.88 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 7.000s 56.564us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 56.334us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 105.855us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 47.869us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 68.545us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 26.758us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 105.855us 5 5 100.00
edn_csr_aliasing 3.000s 68.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 56.000s 2294.127us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 56.000s 2294.127us 100 100 100.00
genbits 100 100 100.00
edn_genbits 56.000s 2294.127us 100 100 100.00
interrupts 20 20 100.00
edn_intr 3.000s 21.309us 20 20 100.00
alerts 200 200 100.00
edn_alert 7.000s 25.168us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 75.774us 100 100 100.00
disable 95 100 95.00
edn_disable 2.000s 26.612us 50 50 100.00
edn_disable_auto_req_mode 11.000s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 7.000s 308.239us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 49.098us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 40.313us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 143.787us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 143.787us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 56.334us 1 1 100.00
edn_csr_rw 2.000s 105.855us 5 5 100.00
edn_csr_aliasing 3.000s 68.545us 1 1 100.00
edn_same_csr_outstanding 3.000s 379.522us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 56.334us 1 1 100.00
edn_csr_rw 2.000s 105.855us 5 5 100.00
edn_csr_aliasing 3.000s 68.545us 1 1 100.00
edn_same_csr_outstanding 3.000s 379.522us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
edn_tl_intg_err 7.000s 275.389us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 20.348us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 7.000s 25.168us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 7.000s 25.168us 200 200 100.00
edn_sec_cm 10.000s 3653.228us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 7.000s 25.168us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 7.000s 275.389us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 130.000s 10790.555us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 20236330630685184585418910444338083316278488366037358960624720564544145113677 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72410669591629948381212699359037783625709093104158331628873716228898217209281 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 22368029161525606999467936757320599551946392470546456021947228242643332145368 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 25364047208857892467376004858402215915075009027330804096829466643272684449887 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 27659190170869949868059301384541240939868274732848542454829804837836519123419 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 4479057371230521415405920130991705296929457045229319043289946356005292623308 234
UVM_INFO @ 3374312888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---