Simulation Results: edn/edn1

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.69 %
  • code
  • 96.39 %
  • assert
  • 98.44 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.220s 51.762us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.060s 20.128us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.010s 35.881us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.630s 693.253us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.400s 48.320us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.510s 101.090us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.010s 35.881us 5 5 100.00
edn_csr_aliasing 1.400s 48.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.000s 385.010us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.000s 385.010us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.000s 385.010us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.340s 29.638us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.720s 35.099us 200 200 100.00
errs 100 100 100.00
edn_err 1.590s 21.006us 100 100 100.00
disable 94 100 94.00
edn_disable 3.640s 500.000us 49 50 98.00
edn_disable_auto_req_mode 8.500s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 8.240s 493.040us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.160s 158.310us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.510s 45.560us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.020s 145.728us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.020s 145.728us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.060s 20.128us 1 1 100.00
edn_csr_rw 1.010s 35.881us 5 5 100.00
edn_csr_aliasing 1.400s 48.320us 1 1 100.00
edn_same_csr_outstanding 1.600s 70.783us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.060s 20.128us 1 1 100.00
edn_csr_rw 1.010s 35.881us 5 5 100.00
edn_csr_aliasing 1.400s 48.320us 1 1 100.00
edn_same_csr_outstanding 1.600s 70.783us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
edn_tl_intg_err 4.660s 477.474us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.300s 75.914us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.720s 35.099us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.720s 35.099us 200 200 100.00
edn_sec_cm 5.900s 339.567us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.720s 35.099us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.660s 477.474us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 108.950s 11996.453us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 6 test runs
edn_disable_auto_req_mode 54322868763298878842392059232479091472790739043346186689034122954444727863963 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65731879002699554856649419363988355031779204662848018966656808832175853101237 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 103201845746337126271960057931646349753038599919684197329808826037714757779470 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65661977352135654875787624332853286492184002085594565727788240563247930399242 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable 86322276701310491465576418877876395321772433837809239084501651722354698200707 85
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111711489123317709192559700723730951889689694138873328731297619307237272037605 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 112333225670314911214787258694727500803210517361520913744147103278101418899872 237
UVM_INFO @ 1809068165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 1272200655516994492198785186707933897651060709923045245010743472973578337436 247
UVM_INFO @ 2222778759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 52964978348816459879683032266888612598428636093151803160274754606735693052599 158
UVM_INFO @ 1472558684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 15197971565624585278396453869511692088335333027066411330274238224269666831369 201
UVM_INFO @ 11996452638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---