Simulation Results: hmac

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 11.000s 410.771us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 34.578us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 373.717us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.000s 633.137us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 1410.161us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 6.000s 21.513us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 373.717us 5 5 100.00
hmac_csr_aliasing 5.000s 1410.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 110.000s 2817.878us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 142.000s 11238.207us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 333.000s 9980.033us 30 30 100.00
hmac_test_sha384_vectors 662.000s 21718.574us 75 75 100.00
hmac_test_sha512_vectors 757.000s 118461.985us 75 75 100.00
hmac_test_hmac256_vectors 30.000s 408.392us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 391.146us 60 60 100.00
hmac_test_hmac512_vectors 31.000s 367.563us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 73.000s 10927.936us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 369.000s 33844.941us 10 10 100.00
error 10 10 100.00
hmac_error 85.000s 35113.075us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 132.000s 7310.653us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 11.000s 410.771us 10 10 100.00
hmac_long_msg 110.000s 2817.878us 10 10 100.00
hmac_back_pressure 142.000s 11238.207us 25 25 100.00
hmac_datapath_stress 369.000s 33844.941us 10 10 100.00
hmac_burst_wr 73.000s 10927.936us 50 50 100.00
hmac_stress_all 1169.000s 64063.793us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 11.000s 410.771us 10 10 100.00
hmac_long_msg 110.000s 2817.878us 10 10 100.00
hmac_back_pressure 142.000s 11238.207us 25 25 100.00
hmac_datapath_stress 369.000s 33844.941us 10 10 100.00
hmac_wipe_secret 132.000s 7310.653us 10 10 100.00
hmac_test_sha256_vectors 333.000s 9980.033us 30 30 100.00
hmac_test_sha384_vectors 662.000s 21718.574us 75 75 100.00
hmac_test_sha512_vectors 757.000s 118461.985us 75 75 100.00
hmac_test_hmac256_vectors 30.000s 408.392us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 391.146us 60 60 100.00
hmac_test_hmac512_vectors 31.000s 367.563us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 11.000s 410.771us 10 10 100.00
hmac_long_msg 110.000s 2817.878us 10 10 100.00
hmac_back_pressure 142.000s 11238.207us 25 25 100.00
hmac_datapath_stress 369.000s 33844.941us 10 10 100.00
hmac_burst_wr 73.000s 10927.936us 50 50 100.00
hmac_error 85.000s 35113.075us 10 10 100.00
hmac_wipe_secret 132.000s 7310.653us 10 10 100.00
hmac_test_sha256_vectors 333.000s 9980.033us 30 30 100.00
hmac_test_sha384_vectors 662.000s 21718.574us 75 75 100.00
hmac_test_sha512_vectors 757.000s 118461.985us 75 75 100.00
hmac_test_hmac256_vectors 30.000s 408.392us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 391.146us 60 60 100.00
hmac_test_hmac512_vectors 31.000s 367.563us 75 75 100.00
hmac_stress_all 1169.000s 64063.793us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1169.000s 64063.793us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 11.000s 12.725us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 15.511us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 724.981us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 724.981us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 34.578us 1 1 100.00
hmac_csr_rw 2.000s 373.717us 5 5 100.00
hmac_csr_aliasing 5.000s 1410.161us 1 1 100.00
hmac_same_csr_outstanding 4.000s 647.565us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 34.578us 1 1 100.00
hmac_csr_rw 2.000s 373.717us 5 5 100.00
hmac_csr_aliasing 5.000s 1410.161us 1 1 100.00
hmac_same_csr_outstanding 4.000s 647.565us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 5.000s 268.165us 5 5 100.00
hmac_tl_intg_err 6.000s 259.722us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 259.722us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 11.000s 410.771us 10 10 100.00
stress_reset 24 25 96.00
hmac_stress_reset 8.000s 10627.178us 24 25 96.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 369.000s 8510.569us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 31.876us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_stress_reset_vseq] wait timeout occurred! 1 test run
hmac_stress_reset 17480379291566689772235932020294221227177323228008681538632188696099929024844 296
UVM_INFO @ 10627177754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---