Simulation Results: lc_ctrl/volatile_unlock_disabled

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.07 %
  • code
  • 93.16 %
  • assert
  • 96.69 %
  • func
  • 89.35 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 88.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.83%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.000s 164.865us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 23.000s 60.895us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 22.000s 39.137us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 23.000s 58.483us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 23.000s 23.856us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 22.000s 36.499us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 22.000s 39.137us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 23.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 112.285us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 1405.607us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 22.000s 13.434us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 110.813us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 25.000s 4191.024us 19 20 95.00
security_escalation 136 140 97.14
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_prog_failure 4.000s 110.813us 20 20 100.00
lc_ctrl_errors 25.000s 4191.024us 19 20 95.00
lc_ctrl_security_escalation 8.000s 1921.482us 20 20 100.00
lc_ctrl_jtag_state_failure 27.000s 4246.154us 19 20 95.00
lc_ctrl_jtag_prog_failure 10.000s 1949.838us 18 20 90.00
lc_ctrl_jtag_errors 29.000s 15604.581us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 9.000s 635.641us 20 20 100.00
lc_ctrl_jtag_state_post_trans 12.000s 5396.654us 20 20 100.00
lc_ctrl_jtag_prog_failure 10.000s 1949.838us 18 20 90.00
lc_ctrl_jtag_errors 29.000s 15604.581us 20 20 100.00
lc_ctrl_jtag_access 26.000s 1563.383us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 15.000s 2819.679us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 8.000s 118.078us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 84.823us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.000s 2116.589us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 20.000s 554.199us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 181.345us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 114.170us 10 10 100.00
lc_ctrl_jtag_alert_test 20.000s 413.266us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 8.000s 607.639us 9 10 90.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 3.000s 20.090us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 58.000s 21449.364us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 22.000s 16.519us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 236.681us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 236.681us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 23.000s 60.895us 1 1 100.00
lc_ctrl_csr_rw 22.000s 39.137us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 23.856us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 101.369us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 23.000s 60.895us 1 1 100.00
lc_ctrl_csr_rw 22.000s 39.137us 5 5 100.00
lc_ctrl_csr_aliasing 23.000s 23.856us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 101.369us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 3709.976us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 3709.976us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 1405.607us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 4634.781us 20 20 100.00
lc_ctrl_sec_cm 7.000s 205.243us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.000s 1921.482us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 112.285us 20 20 100.00
lc_ctrl_jtag_state_post_trans 12.000s 5396.654us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 2126.014us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.000s 2126.014us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 542.916us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 488.877us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.000s 488.877us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 27.000s 6411.581us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 80119338453191676274292083686322925720629310126006031946810029046440991569681 2307
UVM_INFO @ 814765736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93105369366533148536942892102783129307402743177950734941362563012183009301803 2581
UVM_INFO @ 2778706498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6217422524435746479107217634448167900880537749515357808624909781616336774679 209
UVM_INFO @ 2700084498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27698853436722061772486845591751930632607873173887678459388114344192629176908 1661
UVM_INFO @ 1638407214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_prog_failure 28735819571143025031121358064361978159476683559906481264970578929469071492429 176
UVM_INFO @ 230485401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 56621138432764934912110789665014292851985863704901630456422816286896806778293 176
UVM_INFO @ 291432577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 56794388359433866506170978041485699693824270339427109258394659851134758312089 175
UVM_INFO @ 55867699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 14187199292577505362312814165491786041565379655528923367567149005886143785373 157
UVM_INFO @ 10013187226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 60779257913502657114187984389748353096323754538966586041715284890692474597938 774
UVM_INFO @ 470660886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---