Simulation Results: lc_ctrl/volatile_unlock_enabled

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.67 %
  • code
  • 94.18 %
  • assert
  • 96.83 %
  • func
  • 90.00 %
  • block
  • 97.16 %
  • line
  • 97.72 %
  • branch
  • 92.79 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.77%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 531.096us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 17.243us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 13.921us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 1486.165us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 26.444us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 88.139us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 13.921us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 26.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 157.980us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 7.000s 279.312us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 12.465us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.000s 228.729us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 8.000s 1908.490us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_prog_failure 3.000s 228.729us 20 20 100.00
lc_ctrl_errors 8.000s 1908.490us 20 20 100.00
lc_ctrl_security_escalation 7.000s 402.580us 20 20 100.00
lc_ctrl_jtag_state_failure 29.000s 16664.300us 19 20 95.00
lc_ctrl_jtag_prog_failure 11.000s 4795.037us 20 20 100.00
lc_ctrl_jtag_errors 31.000s 13197.376us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 5.000s 268.785us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2955.891us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.000s 4795.037us 20 20 100.00
lc_ctrl_jtag_errors 31.000s 13197.376us 20 20 100.00
lc_ctrl_jtag_access 16.000s 1463.928us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 13.000s 4137.879us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 437.754us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 1824.632us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 10.000s 6812.637us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 5288.932us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 46.326us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 196.468us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 194.584us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 10.000s 1364.361us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 38.768us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 128.000s 41744.654us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 79.175us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 432.356us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 432.356us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 17.243us 1 1 100.00
lc_ctrl_csr_rw 2.000s 13.921us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 26.444us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.302us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 17.243us 1 1 100.00
lc_ctrl_csr_rw 2.000s 13.921us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 26.444us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 21.302us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 504.418us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 504.418us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 7.000s 279.312us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 339.285us 20 20 100.00
lc_ctrl_sec_cm 5.000s 339.312us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.000s 402.580us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 157.980us 20 20 100.00
lc_ctrl_jtag_state_post_trans 10.000s 2955.891us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 498.735us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.000s 498.735us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 7.000s 1291.465us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.000s 353.398us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 6.000s 353.398us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 50.000s 21045.814us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 4014710711130230167807413687493463185491801505597514195146063836608861320525 365
UVM_INFO @ 5449437178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92612187064378497060481114814503843191321368787247782707600630118093701991886 2480
UVM_INFO @ 2252024249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 6066570592795506773703234685280395041388698917234374166563348324843464515167 1306
UVM_INFO @ 458387105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 72459988222208130990275421453527432681814658718355295838384051912041358301990 175
UVM_INFO @ 83158751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 89624806722594353532334943845726060458207596365004639306142747997245522063151 5234
UVM_INFO @ 23725215843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---