Simulation Results: otbn

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.56 %
  • code
  • 86.75 %
  • assert
  • 90.92 %
  • func
  • 100.00 %
  • block
  • 99.37 %
  • line
  • 99.54 %
  • branch
  • 95.39 %
  • toggle
  • 85.89 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
98.77%
V2S
97.26%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 84.124us 1 1 100.00
single_binary 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 8.000s 17.474us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 8.000s 108.962us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 171.291us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 9.000s 57.360us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 43.890us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 8.000s 108.962us 5 5 100.00
otbn_csr_aliasing 9.000s 57.360us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 65.000s 13481.319us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 27.000s 2993.458us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 75.000s 338.727us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 67.000s 794.163us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 129.000s 3818.697us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 260.000s 680.293us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 32.000s 196.651us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 9.000s 55.231us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 19.000s 79.242us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 10.000s 43.399us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 8.000s 83.835us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 605.381us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 605.381us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 8.000s 17.474us 1 1 100.00
otbn_csr_rw 8.000s 108.962us 5 5 100.00
otbn_csr_aliasing 9.000s 57.360us 1 1 100.00
otbn_same_csr_outstanding 5.000s 16.563us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 8.000s 17.474us 1 1 100.00
otbn_csr_rw 8.000s 108.962us 5 5 100.00
otbn_csr_aliasing 9.000s 57.360us 1 1 100.00
otbn_same_csr_outstanding 5.000s 16.563us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 16.000s 87.581us 10 10 100.00
otbn_dmem_err 13.000s 46.752us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 12.000s 62.420us 5 5 100.00
otbn_controller_ispr_rdata_err 47.000s 626.387us 5 5 100.00
otbn_mac_bignum_acc_err 11.000s 314.963us 5 5 100.00
otbn_urnd_err 8.000s 20.185us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 16.651us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 13.252us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 32.920us 10 10 100.00
tl_intg_err 29 30 96.67
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
otbn_tl_intg_err 48.000s 260.459us 24 25 96.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 74.000s 254.045us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 84.124us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 13.000s 46.752us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 16.000s 87.581us 10 10 100.00
sec_cm_bus_integrity 24 25 96.00
otbn_tl_intg_err 48.000s 260.459us 24 25 96.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 32.000s 196.651us 58 60 96.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 16.000s 87.581us 10 10 100.00
otbn_dmem_err 13.000s 46.752us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 55.231us 5 5 100.00
otbn_illegal_mem_acc 8.000s 16.651us 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 16.000s 87.581us 10 10 100.00
otbn_dmem_err 13.000s 46.752us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 55.231us 5 5 100.00
otbn_illegal_mem_acc 8.000s 16.651us 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 32.000s 196.651us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 16.000s 87.581us 10 10 100.00
otbn_dmem_err 13.000s 46.752us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 55.231us 5 5 100.00
otbn_illegal_mem_acc 8.000s 16.651us 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 16.000s 41.312us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 17.026us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 79.000s 156.618us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 79.000s 156.618us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 24.000s 161.688us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 14.000s 154.840us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
sec_cm_loop_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 14.000s 32.202us 3 5 60.00
sec_cm_call_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 14.000s 32.202us 3 5 60.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 6.000s 31.983us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 129.000s 3818.697us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 15.000s 212.210us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 121.000s 1834.172us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 448.000s 6701.967us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 591.000s 6700.738us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 10.000s 157.909us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otbn_stress_all_with_rand_reset 40249922806908835955181250186595642336502175829876302236303127518058320909920 338
UVM_INFO @ 864511652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 59840985812504946758831683513316225355877834878501297323130322053617189749538 332
UVM_INFO @ 761621001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 72802806566617027243777996168244336390171556201397400438104325069737438472485 576
UVM_INFO @ 5958427932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 69442093037841868582970089417320784428391632317621318392686024816912207776975 223
UVM_INFO @ 238591535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45170363607786262664437872923321596043590090440543827895696692404047292530885 620
UVM_INFO @ 1787105482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 55660045370630759678030626219399437716903105727795639385297063852132515813778 151
UVM_INFO @ 120086639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_ctrl_redun 31320163747440705755564177295210390546254620723276965443380466636457570815915 109
UVM_INFO @ 828378464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 54555266485195941770740286478645957703695793988474334043081905499414006942878 118
UVM_INFO @ 252311468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_base_intg_err 114132525384898476484782866807808846209565118911712966958668785837472780714593 111
UVM_INFO @ 161687553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 87874483036021229967011801784713365142274935008938774656372733883825167288498 118
UVM_ERROR @ 9967582 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9967582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 85984741079593767865244119229842318467646215432491522468531706598882507753790 118
UVM_ERROR @ 14097952 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 14097952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 39921623332759049946180444456986875181515578365775415225997140630749046419718 86
UVM_INFO @ 9325315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_escalate 35542211074297297152786548720823120691345570183782520189599095435361255622513 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [otbn_common_vseq] Expected alert (fatal) did not fire in * cycles. 1 test run
otbn_tl_intg_err 57765388573733445908118215335143093495301038922162280931474986243749913542263 88
UVM_INFO @ 16314662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_escalate 70093214326210720879077982199275500979925178753838360915892932814849408791018 111
UVM_INFO @ 21917517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---