Simulation Results: rom_ctrl/32kb

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.11 %
  • code
  • 92.25 %
  • assert
  • 96.80 %
  • func
  • 99.29 %
  • block
  • 93.80 %
  • line
  • 94.91 %
  • branch
  • 89.39 %
  • toggle
  • 84.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.77%
V2S
66.10%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 231.381us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 57.821us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.000s 56.742us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 114.676us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 57.554us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 59.920us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.000s 56.742us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 57.554us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 52.884us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 71.599us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 170.678us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 11.000s 1405.320us 20 20 100.00
kmac_err_chk 1 2 50.00
rom_ctrl_kmac_err_chk 84.000s 200000.000us 1 2 50.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 50.157us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 6.000s 209.372us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 6.000s 209.372us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 57.821us 1 1 100.00
rom_ctrl_csr_rw 3.000s 56.742us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 57.554us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 93.465us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 57.821us 1 1 100.00
rom_ctrl_csr_rw 3.000s 56.742us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 57.554us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 93.465us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 3961.304us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
rom_ctrl_tl_intg_err 34.000s 182.276us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
sec_cm_checker_ctr_consistency 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_checker_ctrl_flow_consistency 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_checker_fsm_local_esc 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_compare_ctrl_flow_consistency 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_compare_ctr_consistency 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 231.381us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 231.381us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 231.381us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 34.000s 182.276us 25 25 100.00
sec_cm_bus_local_esc 2 22 9.09
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
rom_ctrl_kmac_err_chk 84.000s 200000.000us 1 2 50.00
sec_cm_mux_mubi 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_mux_consistency 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_ctrl_redun 1 20 5.00
rom_ctrl_corrupt_sig_fatal_chk 2016.000s 1000000.000us 1 20 5.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 3961.304us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 123.000s 875.294us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 86.000s 6750.376us 17 20 85.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 13 test runs
rom_ctrl_corrupt_sig_fatal_chk 68938136800799140313017491689837454374943653503231963515273692768225578132508 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_kmac_err_chk 64181031086264613553536107244484470313280025845631787017949808687630288599586 86
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 107218677105338446184268445927796638128476431286670295109098659795749707307798 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 50806671670297573029169138560946692852674257413593657657658302691622434753822 91
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 23164826262597601686512702465905587107562301564605094243588591330717321572892 93
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 104276988047114834341466725390608781354785459511678419769798762902283786885856 90
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 50628248655373452256624728979078183533850573644961926914782008204452992313581 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 86010585697933222426022019550531240636727389863292431814722331011512297938723 97
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 75120777141916818602978766900670267596090757617509293756587663704356865561691 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 100293810568522345431825684141665815608992459183079060784370338302707336164479 100
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 38985147508353969993110859862833136130721644549035915284084138407299348614587 90
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 95782051455760655918795073136793610513785297706411964329126411565412940983494 93
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 79743880512760757538378627985402545660935686883561262107790637435017404157644 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 90160446434027596586041991656474201098904996410383824571644918945873832557210 94
UVM_INFO @ 1938666627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 68369606844680497328259577710196377701564343329904678164487325413140216555901 90
UVM_INFO @ 709473247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 55330453798198750741836728416564681394831666639383390162828731211375969952302 89
UVM_INFO @ 1787009826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 26118211776807207238857209312576436071391175951616082250646802583345789229420 94
UVM_INFO @ 1385162161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 21151549077818206716488624273923218133613716655483797610877998456955965948219 89
UVM_INFO @ 63166482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 49750672402627119502354296104951444998154032644082122000248453011157545639443 89
UVM_INFO @ 64687885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:148) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 101308461869552952032157488735391592601496507968995923881257139721665503791469 87
UVM_INFO @ 50115477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 24156933292182383601598034214399969736164522205954619045624614689794599005158 87
UVM_INFO @ 34442561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 46677483161550750684523828303032268081696494366056522309291674537276098425699 88
UVM_INFO @ 21543240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 96648664481066504859429203168672111644912310880427874436620874626625744490841 88
UVM_INFO @ 7415978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 115349163301473122849642713749085191884101298175873170638983441549878804583714 88
UVM_INFO @ 170677757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 106764898866954617008475766139591275149196658577606695304153465600033513894872 94
UVM_INFO @ 2078568867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---