Simulation Results: rom_ctrl/64kb

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 89.67 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 93.52 %
  • line
  • 94.81 %
  • branch
  • 88.64 %
  • toggle
  • 84.74 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
97.18%
V2S
69.49%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.000s 385.000us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 65.403us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 162.185us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 175.102us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 111.686us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 58.742us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 162.185us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 111.686us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.000s 62.091us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 61.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 5.000s 383.224us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 19.000s 1451.037us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 4.000s 58.737us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 4.000s 65.195us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 540.284us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 540.284us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 65.403us 1 1 100.00
rom_ctrl_csr_rw 4.000s 162.185us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 111.686us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.000s 92.854us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 65.403us 1 1 100.00
rom_ctrl_csr_rw 4.000s 162.185us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 111.686us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.000s 92.854us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 7040.578us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
rom_ctrl_tl_intg_err 64.000s 914.493us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
sec_cm_checker_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_checker_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_checker_fsm_local_esc 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_compare_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_compare_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.000s 385.000us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.000s 385.000us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.000s 385.000us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 64.000s 914.493us 25 25 100.00
sec_cm_bus_local_esc 4 22 18.18
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
rom_ctrl_kmac_err_chk 4.000s 58.737us 2 2 100.00
sec_cm_mux_mubi 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_mux_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_ctrl_redun 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 2206.000s 1000000.000us 2 20 10.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 18.000s 7040.578us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 281.000s 1854.029us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 76.000s 18933.624us 17 20 85.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 10 test runs
rom_ctrl_corrupt_sig_fatal_chk 3403316655630680002917585793756638470675229302971647476085000970725979822236 98
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 39609192938716385338445482975393118374899175118807737731420827210992681173362 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 112282414444402561498961192254016456084629044564933802773261023553789426108030 91
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 53409371841949538148068216248890437855491857327637911275123851455083240312598 95
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 94474962628177565876683511434505613386025642010019961803861221691113244023426 96
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 64674852040779916994494177492484781310897761413926373011707515696724026327745 98
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 45531841849917014944349719622530214315961804222702458796954118012052983118804 92
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 81031755895500966874698612993777804784144790958741874535972054044822474253080 88
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 51359549583431088755657694116327431596240474731991225579844079264509106897415 92
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 34783857862572995051704422927946626437302190217799034715577610272340715597343 99
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:148) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 87910560390022968866884083907837261035051876870788597760318553511343129801986 94
UVM_INFO @ 511284942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 76212351927782254272763818257170541215124313067771454625565032857523357041122 87
UVM_INFO @ 34718023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 94424998546204829388296406387179883996672964635567534763549847362952491504505 87
UVM_INFO @ 19174928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 92173093319813772720177487364841563162484763935028791394519158752901673711021 87
UVM_INFO @ 11802825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 24859642766960959562884272849771807086066301849399825833752801398573536947977 88
UVM_INFO @ 64966669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 115719614154235334355806349249505541929948511608571151937588119428476316894824 88
UVM_INFO @ 2391354717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 80185519752211033768467725824045193416585362525476826505094380374940445505778 88
UVM_INFO @ 347839780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 44686941762870724122385945686820352678080158229293666135743600142620780513792 88
UVM_INFO @ 383224392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 17517007155807753786681027929114091065487725326307520358033118717623932240818 88
UVM_INFO @ 12687049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 92297498445515040788293011881051639457809836756945855657730605830230353884774 91
UVM_INFO @ 511779825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 58433559408452780539442514551458117448238869035157802732910649357379176055248 90
UVM_INFO @ 821160266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 1928226094971634350785429501783105517626573883309933226520176515403345412044 90
UVM_INFO @ 51751288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
rom_ctrl_stress_all_with_rand_reset 38535935394419914652982198639909125853817170821395770981410399015175772630683 91
UVM_INFO @ 5636586891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---