Simulation Results: rstmgr_cnsty_chk

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.52 %
  • code
  • 95.05 %
  • assert
  • 100.00 %
  • line
  • 98.41 %
  • branch
  • 98.31 %
  • cond
  • 86.21 %
  • toggle
  • 100.00 %
  • FSM
  • 92.31 %
Validation stages
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
rstmgr_cnsty_chk_test 3.860s 10619.207us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) 1 test run
rstmgr_cnsty_chk_test 68304697784904711282584080523196891685716059873633855239253761883677493628096 175
UVM_INFO @ 1976606550 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1996286550 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 2015966550 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 2035646550 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16