Simulation Results

Simulation Results: rv_dm/use_dmi_interface

31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.88 %

code
84.69 %

assert
96.82 %

func
97.12 %

block
93.96 %

line
94.43 %

branch
83.64 %

toggle
80.31 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		46.67%
V2S		94.00%
V3		5.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	41.000s	1822.684us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	39.000s	587.024us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	53.000s	852.737us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	71.000s	15015.236us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	51.000s	245.058us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	54.000s	1866.771us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	79.000s	16883.461us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	112.000s	43384.540us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	135.000s	132925.927us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	267.833us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	47.000s	326.729us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	586.172us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	45.000s	215.708us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	42.000s	503.085us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	43.000s	1365.394us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	47.000s	79.004us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	45.000s	349.104us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	267.833us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	50.000s	108.636us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	40.000s	395.975us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	586.172us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	51.000s	53.620us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	33.000s	352.084us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	52.000s	222.392us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	66.000s	18919.084us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	76.000s	4445.212us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	50.000s	148.638us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	76.000s	4445.212us	1	1	100.00
	rv_dm_csr_rw	52.000s	222.392us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	48.000s	96.705us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	40.000s	55.111us	1	1	100.00

84/180 passed

46.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	41.000s	1822.684us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	40.000s	751.939us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	46.000s	432.295us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	49.000s	213.666us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	46.000s	1164.571us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	53.000s	3888.964us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	129.082us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	58.000s	8949.215us	2	20	10.00
sba_autoincrement				6	20	30.00
	rv_dm_autoincr_sba_tl_access	89.000s	14922.534us	6	20	30.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	41.000s	141.046us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	44.000s	1147.196us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	44.000s	326.541us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	45.000s	359.540us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	40.000s	5194.720us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	104.000s	15744.145us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	43.000s	57.345us	1	1	100.00
stress_all				3	20	15.00
	rv_dm_stress_all	10802.150s	0.000us	3	20	15.00
alert_test				10	10	100.00
	rv_dm_alert_test	51.000s	223.962us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	50.000s	415.306us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	50.000s	415.306us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	76.000s	4445.212us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	352.084us	1	1	100.00
	rv_dm_csr_rw	52.000s	222.392us	5	5	100.00
	rv_dm_same_csr_outstanding	55.000s	520.135us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	76.000s	4445.212us	1	1	100.00
	rv_dm_csr_hw_reset	33.000s	352.084us	1	1	100.00
	rv_dm_csr_rw	52.000s	222.392us	5	5	100.00
	rv_dm_same_csr_outstanding	55.000s	520.135us	5	5	100.00

V2S

47/50 passed

94.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	45.000s	1176.863us	5	5	100.00
	rv_dm_tl_intg_err	60.000s	2995.428us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	60.000s	2995.428us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	1147.196us	2	2	100.00
	rv_dm_debug_disabled	41.000s	72.780us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	44.000s	1147.196us	2	2	100.00
	rv_dm_debug_disabled	41.000s	72.780us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	41.000s	1822.684us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				8	10	80.00
	rv_dm_buffered_enable	51.000s	486.632us	8	10	80.00
sec_cm_sba_tl_lc_gate_fsm_sparse				3	4	75.00
	rv_dm_sparse_lc_gate_fsm	52.000s	256.295us	3	4	75.00
sec_cm_mem_tl_lc_gate_fsm_sparse				3	4	75.00
	rv_dm_sparse_lc_gate_fsm	52.000s	256.295us	3	4	75.00
sec_cm_exec_ctrl_mubi				8	10	80.00
	rv_dm_buffered_enable	51.000s	486.632us	8	10	80.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	79.000s	1872.282us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	350.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				39 test runs
	rv_dm_sba_tl_access	57132406777362363956926966512491771823197493479836719364788220861350144002156	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23781
	rv_dm_sba_tl_access	63199057490183038167511608964990927725495016166042795658183422982477297069276	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23864
	rv_dm_bad_sba_tl_access	14831564237589531831117930168840401120539386661587328895133289111270123006144	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_sba_tl_access	84829135784486998958764092668046469796303977630576188589396713227890382260253	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_bad_sba_tl_access	106426836264344758885435305716602377483119196976936783736031490792528520227776	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24144
	rv_dm_sba_tl_access	92709695975553354393356404434388182788371517283920243369403126536165986766147	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23877
	rv_dm_bad_sba_tl_access	24043123524829353158391980631950864834970136832146880772447497559865311762338	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23741
	rv_dm_autoincr_sba_tl_access	31316709907420446508203623036216869103038209112689901749524459306708353538741	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @25544
	rv_dm_sba_tl_access	43500279509679885933439482641899986550668195760789613471692345052585279818352	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_sba_tl_access	55811981074761682796093494244773112820590882020055122511655178867796110883434	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23814
	rv_dm_autoincr_sba_tl_access	76136185037343946839729834439783759326402986858126261166663304037871893337615	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23945
	rv_dm_sba_tl_access	60486668323115147509338389209153180089408745979734123497701519065201043208229	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23877
	rv_dm_bad_sba_tl_access	30206421531283368859236436917032794919183499666621712882519059514077017119979	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_autoincr_sba_tl_access	43366949434029615737085596614355467550723438919199353004003279075254659592891	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24029
	rv_dm_sba_tl_access	96459974894502292411734796540309773967172528300377485400235799491461553256390	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_sba_tl_access	83944969488713281290275900490000401964232669890997635166767414765553494496008	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_autoincr_sba_tl_access	98538767497525035179945154979510636570882381634791233644558519260865818242545	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23986
	rv_dm_sba_tl_access	75123135158506413130626147028275518191770954553855311361738793418056252613438	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_bad_sba_tl_access	85638465805344431307616341584916695519642311954989851297432822814952627263581	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24172
	rv_dm_sba_tl_access	114693924868532424445579752996187303802478273833401650315810729093176213243776	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_bad_sba_tl_access	56215861329211464927467896960730750793558866121358985780979902142179291410348	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23736
	rv_dm_sba_tl_access	32016920319971586036162827340392435901833168477612175078030070775758379565425	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23809
	rv_dm_autoincr_sba_tl_access	53347336754996462930018305993869879891787453570597784655682421620935977468216	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23810
	rv_dm_sba_tl_access	25308405006874672315984997417133540366664578569211802493773649878549562506459	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_autoincr_sba_tl_access	81200461066698985790370790232602314599155688810595929933522879730329246147090	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23765
	rv_dm_sba_tl_access	95506643622270660539618097943646946860525610966207035858417645932246921189847	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23788
	rv_dm_bad_sba_tl_access	50743760107267134044431086911851655196375646372996593817481877302565417496178	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23924
	rv_dm_sba_tl_access	68321618078871173307805175795215445733724531700056817436342602611414588126675	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_bad_sba_tl_access	58046396783120968427857600443126722428630075646626609559800665124047158135566	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_autoincr_sba_tl_access	85605262962264308581980572016312033362455234693685199442462627917341973337953	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23761
	rv_dm_sba_tl_access	72358575332078394905257923828142141245746080648770443042061556055028346652692	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_bad_sba_tl_access	77164273647649104718439226258258027930423485908130930574406458661316520406256	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23962
	rv_dm_autoincr_sba_tl_access	34536264367579268989618202650872352265350559879403478497857377595389318694523	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23809
	rv_dm_sba_tl_access	23119962889014104405861582727365413286718850183619389036872404888519070332790	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_bad_sba_tl_access	97204119154315036812522358205913149469842292254655686175393679722772245977077	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10398
	rv_dm_sba_tl_access	93175838302894787428021763879563310016650328397057764576481476838918927873943	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23784
	rv_dm_autoincr_sba_tl_access	86050355710567245905192424729599404858405734586738789081316119745924089454212	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24023
	rv_dm_sba_tl_access	76454098564589179934690430015068745862820208035422526957131048683018102670790	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	71607038094643403220778344464556818030833852353006830653346257304665757916009	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				33 test runs
	rv_dm_delayed_resp_sba_tl_access	72202380602620847800911868647945637182815838697625338051329101538442389117193	107	UVM_INFO @ 84292850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	52735534858803744325574721626079270094547547448318280596249505714289074522278	107	UVM_INFO @ 331963241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	12213505486104657558345349524455492370178888330576944699740266897292980099808	107	UVM_INFO @ 78228620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	87730932835300986816196305211300469538972200809362294933252806965519502474577	107	UVM_INFO @ 82506983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	105423242072210095102573141569725999093192411898857808676033263089688099982484	107	UVM_INFO @ 282572628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	113131293144928628001994572913665359836356496523501467112146132634864165141549	107	UVM_INFO @ 388736792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	109199422144910039317967254231875536321520639283567891557987564780506068021132	107	UVM_INFO @ 93727541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	104076180754589591893405816159368796266496788983565252926120233000369566157675	107	UVM_INFO @ 342675570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57644345630619551807350387864632739581349180840636193366604346825796504237554	107	UVM_INFO @ 196085098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	55546906457619115946936473695410712067436662994324917525899925434416400613522	107	UVM_INFO @ 511300672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93273917117538697253718987857035237727304919348508081327920201115079359565328	107	UVM_INFO @ 129082185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	40714450912544214332662550452715645623538063770301645121013781552931353309103	107	UVM_INFO @ 194824334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	84517283656749820801715469649250319192632344244032803336250668766584768369497	107	UVM_INFO @ 46723837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	113029365898055840946180378409080234807730167494424858412806802255812514947126	107	UVM_INFO @ 326926511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	55579384440252786256801911747822064372277050748043669070789588846172183071193	107	UVM_INFO @ 105372748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	38348715737661847417242220276393354717698496800905994776735433508550428848411	107	UVM_INFO @ 826135341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	83941304825202566599098947923430491127837237478878010943246823869306630280534	107	UVM_INFO @ 182331406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	70557997881704890955191127173377730520681775943716737553853887154542985809020	107	UVM_INFO @ 249947138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85429650895694559680589402566917366028715846029278817263535655870499498744846	107	UVM_INFO @ 118919014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	55046538529756552700329072831721630423134668034056425073943470243457988949031	107	UVM_INFO @ 123723766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	49028788565140636682441648937181484444564291468278180883595964212062896344630	107	UVM_INFO @ 231324340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	11772789366979920857621948711555323835450434945700352111675948666580271985895	107	UVM_INFO @ 99741797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	76500364240973358132143397877541450233755371973774026486316992630552471767713	107	UVM_INFO @ 342283070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	92914287899255700837494071366420035994024665324244053769360438424447148429227	107	UVM_INFO @ 50340941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	59507411112726498969952989076834819694198583819935149307611123580900491034345	107	UVM_INFO @ 208961947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	52613463905258250224286402555814776434540198352867094447567921609838709471178	107	UVM_INFO @ 113665638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	110749239088255975775731270357194170182550315151031923691235431124818284951522	107	UVM_INFO @ 179030646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	663401548452247511253019462956569920821240329262841298943438725354911450460	107	UVM_INFO @ 207817254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	78016753762366682720318334184589208081141683814838888647878459878604739564683	107	UVM_INFO @ 409131940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85059320044490700570110096157701838641905737163000078764108706473685892725178	107	UVM_INFO @ 64778422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	81890744661173548883262648964403612305883045538142716465908428467869517058739	107	UVM_INFO @ 471514674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	50383232157285309013767016515869996752004959355175432066213917498761213806796	107	UVM_INFO @ 150747364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	70715782078735880815375604612802107050975736238293437332193965841491098842826	107	UVM_INFO @ 112024993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				13 test runs
	rv_dm_mem_tl_access_resuming	45874871565090857225315900958644945310722853797016607568006001168864400610039	87	UVM_INFO @ 160193326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	99149846859020970318621493376805184918153482252150898323232813600993032765069	87	UVM_INFO @ 215707904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	95298788941160160885354328462004048889935308702897170467373769083272654066961	91	UVM_INFO @ 2177664293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33567989779725973647528732150504406490381103607955035130371887364098174658361	91	UVM_INFO @ 1887928928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	29020231940939720049901036034688773321954577215390317236386195289093614242118	130	UVM_INFO @ 1332520793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26074191215196944618896372160002252988990752293258746390709359114291403991819	88	UVM_INFO @ 87741517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	70102139515799642783577752703948214892407702422802186029618322013318171764786	92	UVM_INFO @ 217334534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	47197760027146723799845697648422188575110104794406571800365143072386803883787	89	UVM_INFO @ 1278726276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	74616937617404051637871043154588371541093326791014564730803375175442156210010	88	UVM_INFO @ 305238482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	107762471298402418987131934521580808947860704871178748305105289537212167666194	91	UVM_INFO @ 112924629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	50104449450151946572415514344922635062327273157087679403369068627074532298149	91	UVM_INFO @ 839046061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66180823756059829117198281014860303180428368511119126343967558849712220246508	137	UVM_INFO @ 1872282412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	74018293019446203077128205248731248702051697360805246829380491661642800671271	94	UVM_INFO @ 1479612782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				11 test runs
	rv_dm_hart_unavail	58848015456955433281721240371888817485047812529475958012394356758030738989307	87	UVM_INFO @ 359539837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	70535132673469487715979970855013284996828697738203327907576943961617033773246	87	UVM_INFO @ 320089475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	94871167443253172351439272460874127975726828309118623927765822504985054916977	87	UVM_INFO @ 94003459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	20615885266229505814688698521259571185293591479325100536519240136557460755172	87	UVM_INFO @ 186759791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	77204300999890875461275968388576967767392272482973643259592144812054371863261	87	UVM_INFO @ 228464114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	94619885849400810479581141302840782661791597711690992387254784946028316763621	90	UVM_INFO @ 859208051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	79085308890921122105215539864377838128344611427420633450900799697232796646794	89	UVM_INFO @ 2592538812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	6497858663330166105237513266449831767022891096491483357796982473493878894732	95	UVM_INFO @ 369927830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	60891358474959230125856318811829679109187825735396780881214261557538806755629	112	UVM_INFO @ 962252397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45574684583525786003731895453868760224182342267629245804539812041344936230223	89	UVM_INFO @ 412813540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	85827167907490484620478869347384988268796650202596296693223144873940762163512	127	UVM_INFO @ 2103354532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				10 test runs
	rv_dm_jtag_dmi_debug_disabled	73067367012458213342817840742901185737273027384384192429715438804339911552033	87	UVM_INFO @ 141045865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	68179330147062353935130669651710712591327799036755753240177074507243135107465	87	UVM_INFO @ 157240249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32081740405897981316687239599200987382797428572629644651361668840564744911416	92	UVM_INFO @ 137128321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	38332747482997632682978662438887502671673413017426037724664215072588813796291	89	UVM_INFO @ 329695114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	36838830283608889182159037615211659895197406456331852572947649330365574416918	98	UVM_INFO @ 1184881211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104134463245483750439268809528373357297964470324439027921267540419066579927829	105	UVM_INFO @ 484671348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	22053465128821467314808959955789415270467415840076754655355674943554316215635	88	UVM_INFO @ 274378654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	23963127698922488232588678898787146151005117678636381691775162250587783338264	94	UVM_INFO @ 1662835349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93549722800577338246115416565982082418307281232973077458077378652825837901549	89	UVM_INFO @ 761978344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4034180533084215695812663441564371315515729260787205049034890828521485437582	92	UVM_INFO @ 1529322651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				6 test runs
	rv_dm_stress_all_with_rand_reset	1524455095357887367482120127621960050012154697927594405317075735422953980634	122	UVM_INFO @ 4891139582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99412544472995509298612053448548314521015133883725945831610313050587362152006	116	UVM_INFO @ 5794877096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	94547633238383308716028626143737733226731116938731588239624630470793143520155	100	UVM_INFO @ 2584290113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	41669842154154004123382781683756402834994882868014685318656717314806594575841	99	UVM_INFO @ 1451143026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54888070784081188482347402163369306398241178154907222743739269525169687822637	97	UVM_INFO @ 419572909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99618359068539577617320109354518525397893378079516106043214021679083339271591	99	UVM_INFO @ 2390359086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	rv_dm_scanmode	104871757290814893304536973348564502003952685688573305919465297092185468127960	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	110795241235089060921828697913176800117872747785711685425640136436393766090982	95	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	99786948176380503389221986720739885210600089465383662999273639607359461623226	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	42492376406091361198612579891718565619660157693676821673049051736891314532239	None
	rv_dm_stress_all	18641613997567245442005947591661831441516755220232270351222651189861481645560	None
	rv_dm_stress_all	18052232194525502125096663203387882344305206443496137933112458821217904198087	None
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				2 test runs
	rv_dm_buffered_enable	23540165996699904592681347777907878145244084301455910848283838293387453745956	93	UVM_INFO @ 261811249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	66989457105176872794715597988890843941965230578964530915638453359212246048556	91	UVM_INFO @ 500135497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error				1 test run
	rv_dm_sparse_lc_gate_fsm	62952584650420006835291415764700958819755348509787394219698931453067174825027	87	UVM_INFO @ 64155757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---