Simulation Results: rv_timer

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
52.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 956.988us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 66.511us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 22.155us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 1176.329us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 63.090us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 26.018us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 22.155us 5 5 100.00
rv_timer_csr_aliasing 1.000s 63.090us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 15.000s 888.599us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 2020.335us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 404.000s 1634500.250us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 404.000s 1634500.250us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 8.000s 6392.653us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 37.129us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 26.499us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 377.490us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 377.490us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 66.511us 1 1 100.00
rv_timer_csr_rw 2.000s 22.155us 5 5 100.00
rv_timer_csr_aliasing 1.000s 63.090us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 24.588us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 66.511us 1 1 100.00
rv_timer_csr_rw 2.000s 22.155us 5 5 100.00
rv_timer_csr_aliasing 1.000s 63.090us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 24.588us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 38.023us 5 5 100.00
rv_timer_tl_intg_err 2.000s 186.502us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 186.502us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 5 10 50.00
rv_timer_min 3.000s 904.061us 5 10 50.00
max_value 0 10 0.00
rv_timer_max 2.000s 170.612us 0 10 0.00
stress_all_with_rand_reset 16 20 80.00
rv_timer_stress_all_with_rand_reset 56.000s 28384.788us 16 20 80.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 23 test runs
rv_timer_min 87150958678004369802670519194041338376499701957547998736830159814968588626074 85
UVM_INFO @ 121698653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 16002322353963368122582998676372825005586326571367932838093555726762560360242 85
UVM_INFO @ 150190072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107758984597983430355905477308518452690683188453576524951647730280398782331419 84
UVM_INFO @ 254265318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 43768774613175033641332646710267245044537394339819698397102432175145576519749 84
UVM_INFO @ 1109431312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2337600967907931890948863028744460266647061597278289964111299753384059131940 84
UVM_INFO @ 785494505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 8569794577503896898788569437354324853228270536122897036302735605252639102544 84
UVM_INFO @ 904060535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 105372672138383015928627030057756483120126273990614937951853913507324043675806 86
UVM_INFO @ 522083796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50433154749126331808394280393973786001093611121309402445446495100423331264403 84
UVM_INFO @ 73315245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 107393597124266442835829296561701170195141495455477270491347620975536136713156 84
UVM_INFO @ 888598706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 47557090191570077304964550008475807778486656083031063720244958435932375955871 84
UVM_INFO @ 71375239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 114281012809004713915752765244900662974703409316697994729854162478998058988929 84
UVM_INFO @ 1194549646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 72778130672692631110385015574564255007936448744662629643827270327704998644141 84
UVM_INFO @ 2907471843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 51555463667863271309874029878993889685725152401525058547311614918030848566339 87
UVM_INFO @ 62822440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 18964213600011075889705096622686272581899337291794640231347938611634122826697 84
UVM_INFO @ 800579473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 1170819333496780985683360295511445309542016355104373278157076501479850421526 84
UVM_INFO @ 439511715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 70814589386747040343892653741904281519045588359324948277562871313426697623025 85
UVM_INFO @ 175513954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 58446273620193532069156687285102203887727016327599538331396321925848213809153 84
UVM_INFO @ 571447677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 105282835572786585144916183083505574916050463169032515394150062030316714124077 84
UVM_INFO @ 5884506110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 102935100724138544889742686536445291472492600570919404050619850230951929967906 85
UVM_INFO @ 660277877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 46486730971150673545985346679373678992620098439397338456846698526640846985524 84
UVM_INFO @ 100422795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 65075711659558686480265054248322548165354143290082958805591914364214542771362 84
UVM_INFO @ 230577442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 27591411496274500318632801252112623578342192957578199038894679752454192324928 84
UVM_INFO @ 342843708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 77186457551914354845096127645592664237231061452340962949927884472047478379096 84
UVM_INFO @ 346821128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 17955861993289283126567078943784488322697993689345865772199045455334260631877 84
UVM_INFO @ 44535016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 83843185767410189649073590577388745627728453573718740686597580580045745115155 84
UVM_INFO @ 85547778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 2560234957155041250889397531547292552902665632885826097064975743549421941533 84
UVM_INFO @ 42731340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 59264308779153425561816188474815691990440438528400896620665266346902169899384 85
UVM_INFO @ 179032022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 46306452098486850771364855423924676293513442317441072856812477422689878089367 84
UVM_INFO @ 170612439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 27870684404709793995407911535049809283481746724650289139301829013868352500747 84
UVM_INFO @ 88858631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 30944890746159691396863663687603063219708870946615241134458495454211692653013 84
UVM_INFO @ 45508357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 99847746447449041032295802177790818280432153962428299391250040075846250561801 84
UVM_INFO @ 279582578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 52165155582627108886047468637374037611564622280219321042933265120675943147487 84
UVM_INFO @ 49332614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 4 test runs
rv_timer_stress_all_with_rand_reset 72021048695927773497790705093559025412006204690610808827093408248474471118563 110
UVM_INFO @ 2644565684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 34578733404670976700023522525866318799003034739752861496922477005548464473049 123
UVM_INFO @ 1795615644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 70103900877727863909087774794538435585442989080875858035457052821652311192361 89
UVM_INFO @ 290271006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 59914735320926139404146057791194090934483675074539556482084545158289073306263 468
UVM_INFO @ 5341330304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 50154546551975806855059765217362293572680061143205842990846083596039301030651 84
UVM_INFO @ 151596303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---