Simulation Results: spi_host

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 65.000s 8631.729us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 37.646us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 46.178us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 241.038us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.306us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 59.935us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 46.178us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.306us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 20.136us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 79.224us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 24.274us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 8.000s 1081.286us 10 10 100.00
spi_host_error_cmd 2.000s 233.073us 10 10 100.00
spi_host_event 220.000s 43434.507us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 4.000s 166.685us 10 10 100.00
speed 10 10 100.00
spi_host_speed 4.000s 166.685us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 4.000s 166.685us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 956.000s 43726.624us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 242.000s 7109.349us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 134.656us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 4.000s 166.685us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 4.000s 166.685us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 65.000s 8631.729us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 65.000s 8631.729us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 68.000s 15967.283us 10 10 100.00
spien 10 10 100.00
spi_host_spien 34.000s 5006.413us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 138.000s 86242.355us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 7.000s 634.693us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 8.000s 1081.286us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 19.386us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 17.132us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 5.000s 379.595us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 5.000s 379.595us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 37.646us 1 1 100.00
spi_host_csr_rw 2.000s 46.178us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.306us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 39.580us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 37.646us 1 1 100.00
spi_host_csr_rw 2.000s 46.178us 5 5 100.00
spi_host_csr_aliasing 1.000s 28.306us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 39.580us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 108.329us 25 25 100.00
spi_host_sec_cm 2.000s 76.891us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 108.329us 25 25 100.00