Simulation Results: sram_ctrl/main

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.86 %
  • code
  • 95.88 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.36 %
  • line
  • 97.04 %
  • branch
  • 94.64 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 703.080us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 34.156us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 20.306us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 123.584us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.369us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 5036.964us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 20.306us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 21.369us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 282.000s 22471.084us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 124.000s 21113.442us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 60.000s 39482.846us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 206.000s 20788.746us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 243.000s 145821.467us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 104.000s 29342.345us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 60.000s 9042.915us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 53.000s 7336.146us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 7.000s 2882.881us 8 8 100.00
sram_ctrl_partial_access_b2b 481.000s 145677.627us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 8.000s 3878.383us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 2641.269us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 674.310us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 17.000s 3889.298us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 1354.718us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 546.000s 53879.723us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 13.899us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 973.821us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 973.821us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 34.156us 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.306us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 21.369us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 61.995us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 34.156us 1 1 100.00
sram_ctrl_csr_rw 2.000s 20.306us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 21.369us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 61.995us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 88043.537us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 2275.755us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 2275.755us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 3889.298us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 17.000s 3889.298us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 20.306us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 53.000s 7336.146us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 53.000s 7336.146us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 53.000s 7336.146us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 60.000s 9042.915us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 694.949us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 44.000s 88043.537us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 4769.480us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 703.080us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 703.080us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 53.000s 7336.146us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 60.000s 9042.915us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 703.080us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1761.322us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 6441.114us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 3204724178131446300132547441302037685034379670336940132685571184535635762197 86
UVM_INFO @ 661008259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43339311296750005419916066172906797369433502324845758325734297486746489235652 86
UVM_INFO @ 2875182855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 23915699949064004404729161470358777902176845406658697927762760625829476628401 86
UVM_INFO @ 2750237224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 99425511542166966596393204801347988671838418206407085401053105736438074253754 86
UVM_INFO @ 2641466721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 5467165446396316792878653159989215709363382019022487775243515620576129093544 86
UVM_INFO @ 2681914811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 111201646600633590871137819446888339953532602385189196001910616013433592690362 86
UVM_INFO @ 2641269354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 47505320368669261922035409670600258001045080237867643660873673750576288957265 86
UVM_INFO @ 684290318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 4031068277316954105138087515423480376012513343560933777264661404917207249272 86
UVM_INFO @ 696006014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 74219420042445489811931256135148781557848180468567128356854846520459115370421 86
UVM_INFO @ 1352773249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 85216469191196754395349034217495521541752475406114735467842264185782240967996 86
UVM_INFO @ 2626827230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 38805869940334623382378579961527819620957784319117277255682068368526858652980 86
UVM_INFO @ 3878382863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54381024519615854444143441223273286921257564718343482611358260968418781525720 86
UVM_INFO @ 694143808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 15076957517707833320515537760914328645405975737083546361974483757703034930112 86
UVM_INFO @ 2767914192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 80585826297396416275304888783595190376720139592315385013735516162060505588652 86
UVM_INFO @ 4412178058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 75368856558608400330751091521272994165364486571193265187579680848728739828173 86
UVM_INFO @ 2866644541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 85000094576356249976920330168452822804217780603864353362262548687690155667199 86
UVM_INFO @ 1355884250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 115431963086144530061397856244766251543823833461482006268871337505479612018858 86
UVM_INFO @ 692194428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 79027380029414547003458419220777932043454199023240411020326323742444746990685 86
UVM_INFO @ 669965197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 76751903035297745017792033255455492472559577499121501749545480492683121903769 86
UVM_INFO @ 1369394160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 13560504638517447396227339066863556078877597831611156207451270917726284491508 86
UVM_INFO @ 674310457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 63835547424941953118561945590466304151751032552487797073769681344585338251766 86
UVM_INFO @ 664197382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 1394648754287539866294601939138753368434828881237841563867770869645466757215 86
UVM_INFO @ 885718612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 85811378453003044426813242878292606363120715214217628349600273713147639873494 86
UVM_INFO @ 821362781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 34202130238186466622835315650223499519435040870318386044885392555855303879230 86
UVM_INFO @ 666683262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---