Simulation Results: sram_ctrl/ret

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 82.54 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 94.09 %
  • line
  • 95.21 %
  • branch
  • 89.95 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 3.000s 142.791us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 44.862us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.127us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 324.685us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 149.949us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 113.666us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 16.127us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 149.949us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 14.000s 761.397us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 4.000s 353.970us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 14.000s 2099.269us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 233.000s 8622.887us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 9.000s 1111.258us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 27.000s 891.187us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 6.000s 640.982us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 1817.685us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 55.201us 8 8 100.00
sram_ctrl_partial_access_b2b 433.000s 58442.430us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 49.655us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 229.648us 0 8 0.00
sram_ctrl_throughput_w_readback 3.000s 130.496us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 16.000s 9096.105us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 29.131us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 49.000s 4856.699us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 61.545us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 619.832us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 5.000s 619.832us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 44.862us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.127us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 149.949us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.317us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 44.862us 1 1 100.00
sram_ctrl_csr_rw 2.000s 16.127us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 149.949us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 46.317us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 263.360us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 682.021us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 682.021us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 9096.105us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 16.000s 9096.105us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.127us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1817.685us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1817.685us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 1817.685us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 6.000s 640.982us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 92.117us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 263.360us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 141.322us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 142.791us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 3.000s 142.791us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 1817.685us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 6.000s 640.982us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 3.000s 142.791us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 549.071us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 133.000s 8138.302us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 75031437631362691905343180663595127211484963382831737185540351610533132216322 86
UVM_INFO @ 49655321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 92892338978103505481081981096921869113715349827453424673105749457411811646493 86
UVM_INFO @ 229648359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 58939547664254371942909538392341173036221136592178663267189136493662391798511 86
UVM_INFO @ 225297488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 87137235786053298122683906097672407873603210185014435601851589349733375715746 86
UVM_INFO @ 23555343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 46940943813431593536923809498611399895951505620931283297108068565565877423731 86
UVM_INFO @ 25349499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 64813854378306166290689077169805018771665867084323940019232138639664962600886 86
UVM_INFO @ 37180021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 106398567153259673948830824349962366068066088709847696787650951266258674479047 86
UVM_INFO @ 122400792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 23183166889398572908956865996350773985144446989279144650058111519333817317988 86
UVM_INFO @ 37989403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 32060241507486203200329035217042437519667716176201711453949401739867894588164 86
UVM_INFO @ 24026620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 49498097377665193138879735316832368525396519380009202183405144274935519863556 86
UVM_INFO @ 57948266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 72650225471565417430484676137086164379406772737885295967363924351665212688479 86
UVM_INFO @ 27097361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 64290358311207713020472912163564437715038354549787494258798085091232345187905 86
UVM_INFO @ 261850434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 107677884813813966822598360372235423960233593659501087081982233683131338092038 86
UVM_INFO @ 34663852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 91892794246442731325373687503270680614626864063893944904740674279235918250381 86
UVM_INFO @ 93426649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 45683201020154013646885754051299825517705575152205171298153223137003405835479 86
UVM_INFO @ 38614735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 75910782452272261317804961497721325041304006193332720771902961315500715276806 86
UVM_INFO @ 122202422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 8410398919409596661934206637703485819664773721119959569120013319387319984743 86
UVM_INFO @ 414232785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 87587618432827046680063297070913368905362140849601938209022257054302782241206 86
UVM_INFO @ 130496138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 98443902463522993112203692888525492111887020265052376863662099528746607839816 86
UVM_INFO @ 59685798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 52049110015961541461509969226626356541516866067904227868729850814912503829282 86
UVM_INFO @ 78294490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 95857440571303620027146284136411908582320571446994895894264990218793543039292 86
UVM_INFO @ 35403636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30643305269871910765069017695205176204243426313862301174095240005940716349989 86
UVM_INFO @ 37471835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 85671774722903928198275477081774361128629572951937245174470796140509684326100 86
UVM_INFO @ 30621801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 5950246824635031152741334447181833165846750734418513590516692737794265115192 86
UVM_INFO @ 37192787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 13333774264916414827902535940604407878059673983681266263753990804349486044848 88
UVM_INFO @ 24451057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---