Simulation Results: uart

 
31/07/2026 15:00:29 DVSim: v1.49.0 sha: f7401cd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.09 %
  • code
  • 92.73 %
  • assert
  • 98.85 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.47%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 14.000s 5715.405us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 18.422us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 2.000s 16.345us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 214.966us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 17.356us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 36.871us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 2.000s 16.345us 5 5 100.00
uart_csr_aliasing 2.000s 17.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 140.000s 93112.462us 10 10 100.00
parity 20 20 100.00
uart_smoke 14.000s 5715.405us 10 10 100.00
uart_tx_rx 140.000s 93112.462us 10 10 100.00
parity_error 20 20 100.00
uart_intr 126.000s 91220.121us 10 10 100.00
uart_rx_parity_err 208.000s 179839.095us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 140.000s 93112.462us 10 10 100.00
uart_intr 126.000s 91220.121us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 216.000s 120584.207us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 286.000s 162090.656us 10 10 100.00
fifo_reset 199 200 99.50
uart_fifo_reset 183.000s 292399.309us 199 200 99.50
rx_frame_err 10 10 100.00
uart_intr 126.000s 91220.121us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 126.000s 91220.121us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 126.000s 91220.121us 10 10 100.00
perf 10 10 100.00
uart_perf 489.000s 20094.992us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 30.000s 11613.176us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 30.000s 11613.176us 10 10 100.00
rx_noise_filter 0 10 0.00
uart_noise_filter 39.000s 31057.701us 0 10 0.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 73.000s 34191.341us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 20.000s 6843.701us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 31.000s 4501.050us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 1004.000s 170770.349us 10 10 100.00
stress_all 7 10 70.00
uart_stress_all 656.000s 338903.021us 7 10 70.00
alert_test 10 10 100.00
uart_alert_test 2.000s 44.042us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 2.000s 20.037us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 3.000s 48.384us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 3.000s 48.384us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 1.000s 18.422us 1 1 100.00
uart_csr_rw 2.000s 16.345us 5 5 100.00
uart_csr_aliasing 2.000s 17.356us 1 1 100.00
uart_same_csr_outstanding 2.000s 59.823us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 1.000s 18.422us 1 1 100.00
uart_csr_rw 2.000s 16.345us 5 5 100.00
uart_csr_aliasing 2.000s 17.356us 1 1 100.00
uart_same_csr_outstanding 2.000s 59.823us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 2.000s 80.583us 5 5 100.00
uart_tl_intg_err 3.000s 300.716us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 3.000s 300.716us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
uart_stress_all_with_rand_reset 57.000s 4252.275us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 8 test runs
uart_noise_filter 105398445314515791507761407794203419345445054515900557340049299942300517789237 86
UVM_ERROR @ 4002003138 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4002283138 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4002443138 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4002603138 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 79481407151126787498467389806407965502898686865955504892040863032712437589967 83
UVM_ERROR @ 548605899 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 548825899 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 549045899 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 549305899 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 47763624480333618181683844724159990718521262669064458718802560139450676799453 83
UVM_ERROR @ 268129636 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 268329636 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 268529636 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 268729636 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 38333456498000292282796353981183866594982100864875119370782418561814871912018 83
UVM_ERROR @ 424057334 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 480750370 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 480750370 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 513265184 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
uart_stress_all 66725219551106291201600437214435282068933524601025609416772544976161861270349 101
UVM_ERROR @ 114618664188 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 114619300558 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 114620391478 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 114621391488 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 81679291108498651271214115841408249566818701267695647840443880858966497255671 83
UVM_ERROR @ 52182938 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 517183868 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 526183886 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 527683889 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 72924613296624472447300766366489404173291086416908182708401509720782791262062 214
UVM_ERROR @ 4035937850 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_INFO @ 4043073495 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/559
UVM_ERROR @ 4113159071 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 4113159071 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 72176833781161001699156359004470577672079286915962013449102137485464361659478 86
UVM_INFO @ 37425543 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 37745543 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 1/5
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 4 test runs
uart_noise_filter 4442851730414491882262775822270128616528716620829790731406587260350619651939 85
UVM_ERROR @ 3367524224 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 3367544224 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (86 [0x56] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 3577504224 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 3577544224 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_stress_all 77398606895764479893347757842455019508794078334657944411705352857538351085947 106
UVM_ERROR @ 145546694568 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 145546710441 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (83 [0x53] vs 127 [0x7f]) reg name: uart_reg_block.rdata
UVM_ERROR @ 145548186630 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 145548218376 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 70617448467519651046960377822483773867228991167872019585054185152706879429865 88
UVM_ERROR @ 13003420721 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13003441554 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (192 [0xc0] vs 231 [0xe7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 13003483220 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 13003504053 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (192 [0xc0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
uart_noise_filter 15558313719249736849846701026846905523387460273274032521013462813554549214327 83
UVM_ERROR @ 116428421 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 116464135 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 285819923 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 285819923 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 2 test runs
uart_noise_filter 115416494633391666223334280168001138019935029085025473620511984413368489189199 94
UVM_ERROR @ 30678743780 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 30678743780 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 30702374650 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 30702374650 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 58648521767880201730441754047643848422626851325428244631733529080985160667678 94
UVM_ERROR @ 199620889074 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 199629009074 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 199629009074 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 199629329074 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty 2 test runs
uart_fifo_reset 88231338319125620554226594083418597112290497686645544840710228022577597643330 83
UVM_INFO @ 3210674393 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/5
UVM_INFO @ 4770815690 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/5
UVM_INFO @ 27227221805 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/5
UVM_INFO @ 28337506409 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/5
uart_stress_all_with_rand_reset 64185215399419587139318422416369223846985979741343641929725312953210690618113 124
UVM_INFO @ 3577343837 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 3577580681 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
Stress w/ reset is done for run 3/5
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr 1 test run
uart_noise_filter 93117049107168138872559412792022990096179930388760638188325277726782284207810 83
UVM_ERROR @ 22623223 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 209397239 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 209397239 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
UVM_ERROR @ 209397239 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr