Simulation Results: ac_range_check

 
07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.30 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.63 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.23%
V2
97.73%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 48.000s 6275.331us 18 20 90.00
ac_range_check_smoke_racl 20 20 100.00
ac_range_check_smoke_racl 74.000s 5054.086us 20 20 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 128.512us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 314.843us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 36.000s 1440.862us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 28.000s 2547.724us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 26.285us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 314.843us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2547.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 5.000s 241.130us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 57.000s 5654.664us 1 1 100.00
stress_all 8 10 80.00
ac_range_check_stress_all 245.000s 18510.969us 8 10 80.00
alert_test 10 10 100.00
ac_range_check_alert_test 24.000s 13.532us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 41.863us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 156.323us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 156.323us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 128.512us 1 1 100.00
ac_range_check_csr_rw 3.000s 314.843us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2547.724us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 688.684us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 128.512us 1 1 100.00
ac_range_check_csr_rw 3.000s 314.843us 5 5 100.00
ac_range_check_csr_aliasing 28.000s 2547.724us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 688.684us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4909.250us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4909.250us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4909.250us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 4909.250us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 131.000s 15005.481us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 36.973us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 353.644us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 361.000s 15987.121us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 51.000s 1535.795us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 4 test runs
ac_range_check_smoke 51199418283987963116447038207741176160011444971746959030537808486588090324615 4240
UVM_INFO @ 1123662282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 9354917801066911270257355712144518140443159224697139328045088592786029249556 4354
UVM_INFO @ 1958019562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 93422088912799823010609302051321345509932165359864836515516324695474144433691 4859
UVM_INFO @ 1310147518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 45882034098325442410978410989572977219971156993328628533562348548396498003189 4635
UVM_INFO @ 3184922822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---