| V1 |
|
100.00% |
| V2 |
|
89.35% |
| V2S |
|
96.10% |
| V3 |
|
60.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.880s | 286.014us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 13.320s | 151.073us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 143.040s | 1545.307us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 303.650s | 5226.942us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 14.560s | 304.423us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 13.320s | 151.073us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 303.650s | 5226.942us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 351.030s | 28364.597us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 103.900s | 6741.148us | 50 | 50 | 100.00 | |
| entropy | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.133s | 0.000us | 23 | 25 | 92.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 81.020s | 2040.581us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 92.910s | 6894.566us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 90.330s | 15815.985us | 50 | 50 | 100.00 | |
| ping_timeout | 26 | 50 | 52.00 | |||
| alert_handler_ping_timeout | 454.990s | 43495.704us | 26 | 50 | 52.00 | |
| lpg | 92 | 100 | 92.00 | |||
| alert_handler_lpg | 3600.131s | 0.000us | 44 | 50 | 88.00 | |
| alert_handler_lpg_stub_clk | 3600.133s | 0.000us | 48 | 50 | 96.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 5111.280s | 266939.040us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 45.330s | 1817.595us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 7.120s | 72.529us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.700s | 14.074us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.510s | 1559.412us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.510s | 1559.412us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.880s | 286.014us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.320s | 151.073us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 303.650s | 5226.942us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 62.780s | 3129.495us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.880s | 286.014us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.320s | 151.073us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 303.650s | 5226.942us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 62.780s | 3129.495us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 463.870s | 21845.688us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 463.870s | 21845.688us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 463.870s | 21845.688us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 463.870s | 21845.688us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1453.540s | 18018.787us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 106.290s | 5641.768us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 106.290s | 5641.768us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 463.870s | 21845.688us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 56.730s | 1075.947us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 81.020s | 2040.581us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 44 | 50 | 88.00 | |||
| alert_handler_lpg | 3600.131s | 0.000us | 44 | 50 | 88.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 81.020s | 2040.581us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.133s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 23 | 25 | 92.00 | |||
| alert_handler_entropy | 3600.133s | 0.000us | 23 | 25 | 92.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 69.130s | 1238.860us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 6 | 10 | 60.00 | |||
| alert_handler_stress_all_with_rand_reset | 293.140s | 17976.190us | 6 | 10 | 60.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 24 test runs | |||
| alert_handler_ping_timeout | 43153470163455562436305381809620021705870618923372733026614072167248559885485 | 112 |
UVM_INFO @ 14555779888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 1011540108700444683555316111397585947241457575891164865275360368975544983035 | 129 |
UVM_INFO @ 8880644840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 41561018349014090954677039855258979398224014341045166196542789765797048446183 | 84 |
UVM_INFO @ 2033666819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 44712856413247226493306498581028529008066883242830872855729902140687151252483 | 117 |
UVM_INFO @ 35861530176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32053281393514423805324854133509581610812946539835740253350104352073313316419 | 99 |
UVM_INFO @ 7009060782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 7607116016975415614457586013373198220636371920639071678789944612696767581977 | 84 |
UVM_INFO @ 170067334436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 88965575508760946042239095000755387752428274118201313138082830205573923337154 | 87 |
UVM_INFO @ 11706915126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 32920767384241439987371653946758738445361383187967610913077586638322705385309 | 87 |
UVM_INFO @ 3133217707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 5337420440259569732027776889038927104225779166743413962032985695849290175737 | 85 |
UVM_INFO @ 824304188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 111816673088627597541526156570703098421800197010970428964044531224387932234682 | 108 |
UVM_INFO @ 4590958007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 152513426410815992053694015946571690530350240680960995510257495425342284776 | 123 |
UVM_INFO @ 28013375678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4315430748598418271948053270036319794261193999855450493310332315489685890800 | 108 |
UVM_INFO @ 5923250639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 29851739834229080656277890438829573309161212762252311524233322265824472576674 | 84 |
UVM_INFO @ 974080159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 111298694516567693977900702002268897434795769898870937784299320087503598082549 | 103 |
UVM_INFO @ 3300809900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7799907557935279407891743335256597118646875307391892919131114843176568806233 | 96 |
UVM_INFO @ 3461760086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99516403805921794145078413422916905149855516247750233553884719554294835576847 | 102 |
UVM_INFO @ 10434937773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 37704667644935793135659842632121497568254259441928731842129733872661338021346 | 105 |
UVM_INFO @ 13017155812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 108102234727047164106484158382443623300565315346571321156042922743820699166643 | 90 |
UVM_INFO @ 2758991554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70887629759471392634054613495425184487765343601300200383458875664699379629603 | 96 |
UVM_INFO @ 63031391046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 35872722765875874298686361230177454681450754780024653868974337375215571035201 | 108 |
UVM_INFO @ 2926343619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 672168059649378454483812343221189249562299909951900814190976529223424095538 | 87 |
UVM_INFO @ 2170619379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 66127195270292213827440955516555180209495109788016960484591365821099688849375 | 81 |
UVM_INFO @ 74906419856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 22413782659625329776929246192825175728681158445462142425482421875745876446778 | 84 |
UVM_INFO @ 727206138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31468161979011956321628938361850435202532677543444497989162368735241677337914 | 87 |
UVM_INFO @ 2283649410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 37454838764560297305065511160911291661157720442072910046961023796211672774827 | 222 |
UVM_INFO @ 1738538964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 70395395559985519656796259987491824291324738117830007662064944231206900910890 | 168 |
UVM_INFO @ 278130837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 50836174921150226938755073354824554214408604876045982189159340939382485779598 | 212 |
UVM_INFO @ 2045840500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 92576532719499664884660181089312857224576305292133612219188251591876300450273 | 160 |
UVM_INFO @ 513739211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 9308290284472031765745220379795244747177936608185498640217718483368465970391 | 164 |
UVM_INFO @ 399178357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 81503981127587472347353859973690169669612040757648071379984659958836596640050 | 224 |
UVM_INFO @ 356603112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 40815240683033854849421021330712830131825405258323081485325338751081336347291 | 182 |
UVM_INFO @ 580163940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 46113184649948838336739561122005807948517973239860455919583691052254675852288 | 126 |
UVM_INFO @ 1813130100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 17617975541611888390992516452533885977889703326510993651031056482230659105295 | 120 |
UVM_INFO @ 669286695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62015377845251303305194897912236538150089019678929488632696676818085435487004 | 174 |
UVM_INFO @ 683179466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 99959044868545888672030769128978267990230017406595838682824707034926246814810 | 222 |
UVM_INFO @ 411823208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 32140767043268611221206472496031344720382684000313004383063563386304983868320 | 216 |
UVM_INFO @ 145727629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 36948993832858014723048750455391143018251789692602886999313640158558552475736 | 230 |
UVM_INFO @ 157897623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 15181015457586325552075259562229208285049293846645658999827946239229096259982 | 222 |
UVM_INFO @ 200022483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 47868518028159575959929113911030173116228049983697894434674645036468063322543 | 194 |
UVM_INFO @ 2542781919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 88997544564694667178014883593082053760551723299547811240091770541058694131545 | 198 |
UVM_INFO @ 543926622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 53167951634003473852370471541003691849348948451558327999772261776604110406521 | 212 |
UVM_INFO @ 535995807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 77090297266003600518632306438415645235074258666221810566975363048061694223163 | 210 |
UVM_INFO @ 158097409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 110039413317260485950020456380344587742353349861547192145460309335944762969446 | 140 |
UVM_INFO @ 116222299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 48850243508590419601381270430124328930179824855631384216950930519084133761388 | 224 |
UVM_INFO @ 1817595066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 6 test runs | |||
| alert_handler_lpg | 92474720049309080051516724893259326792323597609478826522318289465725016655024 | None | ||
| alert_handler_lpg | 31272295994494612280788302428988198372423880552780200295000888433593184822456 | None | ||
| alert_handler_entropy | 25197753409924182923716183197639240208213253524294359927047383864141743730560 | None | ||
| alert_handler_lpg_stub_clk | 1268366462706478824601542363087988942655736066527212974786273176488176269289 | None | ||
| alert_handler_lpg_stub_clk | 58501092140563040823315078933976630910014190798993202915720045930562017022277 | None | ||
| alert_handler_lpg | 109572832952070249246380255047101350364502447355949648987467217179176295524686 | None | ||
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 4 test runs | |||
| alert_handler_stress_all_with_rand_reset | 108635655560594257380576518203019848142081899208336666213082237806042139834993 | 178 |
UVM_INFO @ 8383620437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 75900293942555197590733819156427237193340818926354854931601483068359046914650 | 121 |
UVM_INFO @ 9163276819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 63980608221776922466648272204778888717436160888032048236645900035925780493014 | 143 |
UVM_INFO @ 13321635336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_stress_all_with_rand_reset | 27470367364076139795997467279550911034114430366850204208961367289688689596327 | 92 |
UVM_INFO @ 2760589627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 2 test runs | |||
| alert_handler_ping_timeout | 79580096867413395337271188599077112309858213937841817332779548358225524352756 | 80 |
UVM_INFO @ 2571999749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| alert_handler_ping_timeout | 19508246529549297895732030123930173259441808471020960098951960257987241475941 | 80 |
UVM_INFO @ 988512746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.loc_alert_cause_* | 1 test run | |||
| alert_handler_lpg | 94667592845752358293445965677877806542331731228459002929180711196358959563884 | 80 |
UVM_INFO @ 1632927826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 1 test run | |||
| alert_handler_entropy | 34564402780083365421513777999967564873616534643871350710898372554571258394464 | 80 |
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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