| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 3.000s | 601.220us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aon_timer_csr_hw_reset | 16.000s | 1173.939us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 520.370us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aon_timer_csr_bit_bash | 24.000s | 7262.423us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aon_timer_csr_aliasing | 18.000s | 557.274us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 3.000s | 526.850us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aon_timer_csr_rw | 2.000s | 520.370us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 18.000s | 557.274us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| aon_timer_mem_walk | 1.000s | 283.499us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| aon_timer_mem_partial_access | 2.000s | 414.536us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 70.000s | 36530.536us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 4.000s | 751.029us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 252.000s | 185969.119us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aon_timer_alert_test | 23.000s | 348.694us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| aon_timer_intr_test | 3.000s | 468.565us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 5.000s | 458.310us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aon_timer_tl_errors | 5.000s | 458.310us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 16.000s | 1173.939us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 520.370us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 18.000s | 557.274us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 8.000s | 2562.095us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aon_timer_csr_hw_reset | 16.000s | 1173.939us | 1 | 1 | 100.00 | |
| aon_timer_csr_rw | 2.000s | 520.370us | 5 | 5 | 100.00 | |
| aon_timer_csr_aliasing | 18.000s | 557.274us | 1 | 1 | 100.00 | |
| aon_timer_same_csr_outstanding | 8.000s | 2562.095us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| aon_timer_sec_cm | 9.000s | 8178.341us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 20.000s | 8594.471us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aon_timer_tl_intg_err | 20.000s | 8594.471us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 3.000s | 572.538us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 4.000s | 668.030us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 10.000s | 3193.526us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 3.000s | 725.150us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 26.000s | 4248.939us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 48.000s | 26451.574us | 15 | 15 | 100.00 | |