Simulation Results

Simulation Results: clkmgr

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.56 %

code
79.71 %

assert
94.83 %

func
76.15 %

line
91.44 %

branch
93.99 %

cond
88.13 %

toggle
100.00 %

FSM
25.00 %

Validation stages

V1		60.87%
V2		67.52%
V2S		30.48%
V3		0.00%

14/23 passed

60.87 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	3.490s	166.161us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.180s	17.078us	1	1	100.00
csr_rw				1	5	20.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	4.600s	138.969us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.750s	52.251us	1	1	100.00
csr_mem_rw_with_rand_reset				1	5	20.00
	clkmgr_csr_mem_rw_with_rand_reset	2.980s	82.459us	1	5	20.00
regwen_csr_and_corresponding_lockable_csr				2	6	33.33
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
	clkmgr_csr_aliasing	1.750s	52.251us	1	1	100.00

79/117 passed

67.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	3.840s	194.079us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.880s	63.432us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.900s	78.889us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	3.490s	166.161us	10	10	100.00
frequency				1	10	10.00
	clkmgr_frequency	1.340s	43.019us	1	10	10.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.000s	13.389us	0	10	0.00
frequency_overflow				1	10	10.00
	clkmgr_frequency	1.340s	43.019us	1	10	10.00
stress_all				0	10	0.00
	clkmgr_stress_all	6.110s	328.047us	0	10	0.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.640s	54.069us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	9.700s	803.115us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	9.700s	803.115us	25	25	100.00
tl_d_outstanding_access				3	12	25.00
	clkmgr_csr_hw_reset	1.180s	17.078us	1	1	100.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
	clkmgr_csr_aliasing	1.750s	52.251us	1	1	100.00
	clkmgr_same_csr_outstanding	1.150s	10.684us	0	5	0.00
tl_d_partial_access				3	12	25.00
	clkmgr_csr_hw_reset	1.180s	17.078us	1	1	100.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
	clkmgr_csr_aliasing	1.750s	52.251us	1	1	100.00
	clkmgr_same_csr_outstanding	1.150s	10.684us	0	5	0.00

V2S

32/105 passed

30.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	30	6.67
	clkmgr_sec_cm	131.160s	10020.542us	2	5	40.00
	clkmgr_tl_intg_err	2.740s	128.060us	0	25	0.00
shadow_reg_update_error				18	20	90.00
	clkmgr_shadow_reg_errors	2183.970s	200000.000us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	clkmgr_shadow_reg_errors	2183.970s	200000.000us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	clkmgr_shadow_reg_errors	2183.970s	200000.000us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	clkmgr_shadow_reg_errors	2183.970s	200000.000us	18	20	90.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	2.060s	76.332us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.740s	128.060us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				1	10	10.00
	clkmgr_frequency	1.340s	43.019us	1	10	10.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.000s	13.389us	0	10	0.00
sec_cm_meas_config_shadow				18	20	90.00
	clkmgr_shadow_reg_errors	2183.970s	200000.000us	18	20	90.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.380s	79.522us	10	10	100.00
sec_cm_jitter_config_mubi				1	5	20.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
sec_cm_idle_ctr_redun				2	5	40.00
	clkmgr_sec_cm	131.160s	10020.542us	2	5	40.00
sec_cm_meas_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
sec_cm_clk_ctrl_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.220s	15.399us	1	5	20.00
prim_count_check				2	5	40.00
	clkmgr_sec_cm	131.160s	10020.542us	2	5	40.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.000s	5.849us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	5.500s	189.842us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				29 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	20216911545521587578370886358971472426523689423361932486764543334457825465916	75	UVM_INFO @ 7845285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115101197431435616862764618171326141032502623736269731065790906347001551099108	78	UVM_INFO @ 14767951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	23048484848932849957541899853569898033690704009124116804894061717780464444060	75	UVM_INFO @ 14560034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	91127377773083403698568327014725699831131073689883699318506721727388198148586	76	UVM_INFO @ 4257067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	5443682181497227847341752827958130216731439248695357983809961322908038678564	75	UVM_INFO @ 2277696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	40844458230103933256101494744727632188423550218967291282458823706723011377625	78	UVM_INFO @ 6213490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	14982660972932900509998936116611055294312879467710577019065624736907061484291	75	UVM_INFO @ 7262820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	34891876161040452815066325165413667179948624813833755606204479401592309012728	82	UVM_INFO @ 99588054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	23766143429017369393025302390523108880077924038748378553487895837418391808111	75	UVM_INFO @ 5300128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	28842536013063158588102296833386731577383131573298714428723159848964578199950	78	UVM_INFO @ 6820445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	16982248429413579127950411051164760640148436964523781834738011742979849861964	75	UVM_INFO @ 11010299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	98895658103395851472814169925982176982307503297990047063511541741078680944875	75	UVM_INFO @ 5783625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	62423160350418488291746336211178636769821545533561128040589668665905943812199	82	UVM_INFO @ 9448496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	113796104732800697309715198560607348518338225212402288295339171340316362700116	75	UVM_INFO @ 2464707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	61248599822442785144679632008432402698124829298403370152390265398656691446137	85	UVM_INFO @ 12096113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52752282582936882635841407731927782546967036840898548888586996877016470981657	75	UVM_INFO @ 4834162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	21659020590083386838399695340723305390727314585426512128781565768900207912404	93	UVM_INFO @ 15930421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	65815684652605743016341068680939283024743373175408695637924804540291019302607	75	UVM_INFO @ 8774229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	98566322024710191527928715558432715246826375845600013140255718163444410129292	75	UVM_INFO @ 4906846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	11768816399472678726679364040824527959961864194890910258321252659359734098278	96	UVM_INFO @ 22143587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37887851029778754672031894135629795469270021110693167418916052630888115519902	75	UVM_INFO @ 25640945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73064393577643954258824362967978294433354704874707518114392617346168196538570	97	UVM_INFO @ 15038015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	17203717327506005428720480878784913067792298578758663447029331878956411006656	75	UVM_INFO @ 76331676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	59836320619874023508874698739894495330465003830234554250353891791363233665198	75	UVM_INFO @ 8082366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82689707982942691831663486357615933122579253131129413245934768167360669795622	108	UVM_INFO @ 128059524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	86441313728189581937087430027246934195637482332515312197175745889537365393255	75	UVM_INFO @ 26522415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	28042510619274912450070970259134011349246338803944171922556253831480643985124	75	UVM_INFO @ 2472349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	52579268701580881577863952203039106796263013853950309111944027270094667524855	82	UVM_INFO @ 7541859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50550725372175053576634652074531065125697433317548344324922214742291751127736	78	UVM_INFO @ 3463002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				24 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	55912396512402302806652425111251896955404170805912125865036345876213294602118	75	UVM_INFO @ 24278433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	11686738158175654840913528193147117492013412375281373799331379827302846456752	86	UVM_INFO @ 26972035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	19078445986458682103107171674987777681795416726645345082684324850833203689617	76	UVM_INFO @ 27302457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	84340935701301444604263280699567098135756031225075247825989248735967154348123	76	UVM_INFO @ 5437106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	18233289598428798309516517389309760299915192506961843435492323707701860279523	82	UVM_INFO @ 82458590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	82582156320111767582981728895219168773509292040444645039053802897891230303010	75	UVM_INFO @ 8638062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	36924794778469987467565009687854966572989475971981037181427606766328336276464	75	UVM_INFO @ 1995247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	10389340032273517198476073020225642666648485670905425161648146920184259944927	75	UVM_INFO @ 1692335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	85482192061539526734577588666906656486085664520953562374092827028862723021152	75	UVM_INFO @ 10088981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	48692294387959870698044204259076788042040124781196505570928470521106642929322	89	UVM_INFO @ 12560994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	7424533146031262288706135304445309328834739473862993628714013609422867148836	75	UVM_INFO @ 2913751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	53424743756719280624451133453783958797236939005407657665933489609108498594382	89	UVM_INFO @ 24130594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	114367614107850044579035166479946613404552241975833502962533637922046436653749	75	UVM_INFO @ 12267695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16302875085279806702857308727087997676846862455620740377863679785019984004498	75	UVM_INFO @ 1607075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	28838570954383406793573688002995524272465826337788331842302110322248554561641	85	UVM_INFO @ 4293611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	81113628255576126187601000810769343905401417068277442388364791788041018545478	75	UVM_INFO @ 52459269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	59961422610292450582903790243044867524643425410660742077644748166592323472063	75	UVM_INFO @ 3121296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	8050724414164685579347340564468491272613855064226522034898894117092443376717	75	UVM_INFO @ 6072151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	33952909712263975082374592753617518379531750023848139146865782762965396352444	86	UVM_INFO @ 5121404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	84489430141864967532741488714315079471050578486206468021565536730950437557502	75	UVM_INFO @ 10311952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	115750451617305697993236261201935797555121704218146087318256303292288314063309	86	UVM_INFO @ 16490128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	74850016236064550684000232565466136509302660754555774004916511615661793908360	120	UVM_INFO @ 23119620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	111249802153652453823157933552839920436452643128650741643671938932483589873500	82	UVM_INFO @ 2109137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	93648430700586424584206604625223329237064193107296863714247374964413311628217	75	UVM_INFO @ 2340949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				20 test runs
	clkmgr_frequency_timeout	7017684016252668699900007702977304473914574926897411707548131393391308090954	77	UVM_INFO @ 4753906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	53402701470798795579265062412424817307133223394997392349761754388982131790729	79	UVM_INFO @ 7041428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	27282458222856718050279532862343509099187767671012519267960117158172147453052	78	UVM_INFO @ 4522734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	3314854040247311070266126822845954953934697881579287194294033387363276001402	79	UVM_INFO @ 19400794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	104033086750186920382710277430920645459666708718700808552837335645493527711856	78	UVM_INFO @ 5044177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	50400303252858072455916347995604870526683643230482089737989555176914336718251	78	UVM_INFO @ 3151959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	93762833421972983689058620804758701449709141599154419339328382413120211154208	78	UVM_INFO @ 1898618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	61881762230766444033257495894893859548329755781832498174272841231696983928078	79	UVM_INFO @ 21266414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	89096782117248026181898301809943350410749687929242167916229037844688869779838	201	UVM_INFO @ 328046540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	3753475709985011139385793851456761320203154324390520952029027979910075358388	78	UVM_INFO @ 3842907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	68668586849833405323875035787153821817546956131180029150524562686982792818475	115	UVM_INFO @ 30031469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	78480560183797036599228603649918739703103396074742533942873478554241215858829	78	UVM_INFO @ 13388884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	29932479143050181631527380286868859267584145631596700775171737844204889395498	77	UVM_INFO @ 3000122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	94410319544214585749036976039184170941566604418471454498235828800116485002465	77	UVM_INFO @ 4006244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	36718132043395796113743714347970461181220547658395671936723001390753140782629	78	UVM_INFO @ 13991608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	70260258632722863098104325422561598457947034957993153844245567671900591372850	78	UVM_INFO @ 4953438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	75969343543626067704767767953482614358819515557187763556409155588408663576909	78	UVM_INFO @ 2987559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	55545004008816053726993104798465740516031012889112421884626548187095131996274	97	UVM_INFO @ 21139690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	30504655872951332353451676185181946447713612467512427363231833731162240957318	77	UVM_INFO @ 11339675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	8568487415051323096898533884146507011063165758139773341017253557794339789523	77	UVM_INFO @ 3285091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				19 test runs
	clkmgr_frequency	16370418831607015035418779814829563718079406741646686278702746053182188408612	75	UVM_INFO @ 6043281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	93797672080215411202851827104313128448858557917822040893019159384004775451405	76	UVM_INFO @ 33116909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	57107447059278492650847852992568497204685450572877259246178482046842177270561	75	UVM_INFO @ 20913705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	61493717534383959296797328530675974035111808723232148577344118655627600943923	76	UVM_INFO @ 15092519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	9187172867559441988912923281813340206907156745564165497039534363630073753824	78	UVM_INFO @ 53875384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	24847882053793198178485318483474906451422833191809805048979696666519319691428	75	UVM_INFO @ 11876756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	18878271115884239366126208274985449394215947075975966711184054245449089073890	75	UVM_INFO @ 7082569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	41201604974623716822764071941620587920221058997938098268707188719216186330792	76	UVM_INFO @ 5362857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	103047222701583272132503543022075788222179224889994457825269395014275059372682	75	UVM_INFO @ 14618876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	74184149808006686915843335815477222882110810007234472768020796736944225597858	78	UVM_INFO @ 183280470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	75005172336180703021773344402989484714382871740083866942007531315132197416842	75	UVM_INFO @ 5509137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	89841480507736702279002103317220408162627869070176259674813642305777481142212	77	UVM_INFO @ 7024168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	48702247781386410258611580447178017236262523424282704969153097610953525223528	75	UVM_INFO @ 6746941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	46468750619752595199834903311684106668206427827084409252127983856343084381686	78	UVM_INFO @ 9243596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	36247891278894195071787736769257330469294810892317403174954522356763518137082	148	UVM_INFO @ 130574815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	62729146951884001426690411689818450710658675838082624901807307740108981641233	76	UVM_INFO @ 7963725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	20956958440133866013854369875954003972962371065006101218253867102729287460173	75	UVM_INFO @ 14358791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	22657645679525159215899698318608238574418892318352484999906425647523857009023	180	UVM_INFO @ 189842263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	57730042600947473901914166901018721737630659059421318978239193160323277810239	76	UVM_INFO @ 6571700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				7 test runs
	clkmgr_regwen	99949396382535113512817981005632235495780759618216420994207022215612552429817	74	UVM_INFO @ 5849121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	8527924813748882878751336012483435819469317451955092584036239447076441612771	74	UVM_INFO @ 2455678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	95698232116588482921279160637711918654047812187068599273755041457431621018525	74	UVM_INFO @ 3341781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	48308258953600386994703376148415920501548764876296399509383412872991421013316	74	UVM_INFO @ 3583962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	91861884913763991490118811176085876190213014199766130585580907087033492993832	74	UVM_INFO @ 3122427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	32266149296587553853089338316249356609911719643442209421754408530096653649938	74	UVM_INFO @ 10576195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	40851633967303545235814197940055939359999634544250110912593669104034078947519	74	UVM_INFO @ 7460008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	68393538068762603694009039187616198259649558072808792558520457372132847964508	75	UVM_INFO @ 6057068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	82988197933677007451207104781063546690009243757477744553436824646497337492220	75	UVM_INFO @ 2552637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	5971270110719124325815015898692533216275732882922213169637780195286282501890	75	UVM_INFO @ 8399534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	82855691332519751236713283251819920885758296060474057522814684192818547606309	75	UVM_INFO @ 11189151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	88303098904458701556909430693164014313704169831987119936093802372702221530729	75	UVM_INFO @ 10684056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				3 test runs
	clkmgr_regwen	46518415110070759714762505701820041442612318959895938701878872289908479116175	74	UVM_INFO @ 6630368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	32348067729633498651268089296811886615643441589632755853517490934831762507884	74	UVM_INFO @ 4097094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	43409908025078420327664540643336864783355154369368477164739955312783168486479	74	UVM_INFO @ 6161942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	83675747051234310023903100463077739729656246684751585975239441738504819626699	77	UVM_INFO @ 2939423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	67703883638247046556933181045534158648144651555495534678694514088849874892683	143	UVM_INFO @ 99134353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	clkmgr_shadow_reg_errors	77126971302835942687666390150405340900417068719799091134591867011211149247311	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	70021628985584352099934293808535336397079427353879696376094349531579136735551	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	101628438861080565862973540158082540400032448457078689676922826859706809668529	75	UVM_INFO @ 138968516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				1 test run
	clkmgr_sec_cm	33060781706742944581392988638186511151184812134680332137491015148863383824531	94	UVM_INFO @ 10020541801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---