Simulation Results

Simulation Results: csrng

07/08/2026 15:00:34 DVSim: v1.49.0 sha: 41d86cc json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.81 %

code
96.17 %

assert
97.16 %

func
91.09 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		98.83%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	5.000s	220.289us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	35.000s	239.439us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	33.000s	17.552us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	71.000s	2672.672us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	35.000s	113.514us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	33.000s	16.744us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	33.000s	17.552us	5	5	100.00
	csrng_csr_aliasing	35.000s	113.514us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	24.000s	80.277us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	52.000s	2922.816us	500	500	100.00
err				499	500	99.80
	csrng_err	302.000s	10000.872us	499	500	99.80
cmds				4	25	16.00
	csrng_cmds	329.000s	30570.794us	4	25	16.00
life cycle				4	25	16.00
	csrng_cmds	329.000s	30570.794us	4	25	16.00
stress_all				23	25	92.00
	csrng_stress_all	611.000s	16399.147us	23	25	92.00
intr_test				10	10	100.00
	csrng_intr_test	3.000s	83.229us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	33.000s	54.097us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	14.000s	745.193us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	14.000s	745.193us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	35.000s	239.439us	1	1	100.00
	csrng_csr_rw	33.000s	17.552us	5	5	100.00
	csrng_csr_aliasing	35.000s	113.514us	1	1	100.00
	csrng_same_csr_outstanding	7.000s	358.988us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	35.000s	239.439us	1	1	100.00
	csrng_csr_rw	33.000s	17.552us	5	5	100.00
	csrng_csr_aliasing	35.000s	113.514us	1	1	100.00
	csrng_same_csr_outstanding	7.000s	358.988us	5	5	100.00

V2S

1270/1285 passed

98.83 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
	csrng_tl_intg_err	33.000s	1710.398us	25	25	100.00
sec_cm_config_regwen				18	30	60.00
	csrng_regwen	3.000s	102.645us	13	25	52.00
	csrng_csr_rw	33.000s	17.552us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	52.000s	2922.816us	500	500	100.00
sec_cm_intersig_mubi				23	25	92.00
	csrng_stress_all	611.000s	16399.147us	23	25	92.00
sec_cm_main_sm_fsm_sparse				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	52.000s	2922.816us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				699	700	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
sec_cm_constants_lc_gated				23	25	92.00
	csrng_stress_all	611.000s	16399.147us	23	25	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	52.000s	2922.816us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	33.000s	1710.398us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				699	700	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
sec_cm_aes_cipher_ctrl_sparse				699	700	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
sec_cm_aes_cipher_fsm_local_esc				699	700	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
sec_cm_aes_cipher_ctr_redun				704	705	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80
	csrng_sec_cm	4.000s	148.619us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				699	700	99.86
	csrng_intr	24.000s	80.277us	200	200	100.00
	csrng_err	302.000s	10000.872us	499	500	99.80

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3600.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				19 test runs
	csrng_cmds	24467132276758491677178622798727204939687092377825998912927392004777423120916	110	UVM_INFO @ 165823341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32464207330172390207536316179267505824450200169116718432050599298283974805372	110	UVM_INFO @ 199939446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	26848991778896184541006997940629889270374125846733416361930004983949123020909	100	UVM_INFO @ 79911860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	64450328587752272695634222083498798421712144836052449457013728028729447085075	100	UVM_INFO @ 376902863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83318715315579288178129015093383255069630652694752007076423639762553934983439	100	UVM_INFO @ 78011653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10992893732729657193640871239532583289295821568051121129840364521383843852516	100	UVM_INFO @ 93049711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56726308970259316975178636035760761848623958570945933683280276034751527966442	100	UVM_INFO @ 187650406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48700193083343196444260141062471861464731846586406287137137577997125079681618	100	UVM_INFO @ 56877006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99878119933942110600527001343447461680459389077393309767532508245121589516327	100	UVM_INFO @ 185564337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54883202274472923925820497060561480652831651325679494749778545024562617392992	100	UVM_INFO @ 79871582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3969279293499812699575163596548279566992815397898719562049905071611264336007	119	UVM_INFO @ 112414037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77874507954990920691043959866221995703901375015484571035024984062341661517971	100	UVM_INFO @ 388071876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	28156219347220225034959044826880372134365832462282714321327378986465313968063	100	UVM_INFO @ 328031332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36172383912524875451401109895386403464249666794837763092752365076434207964656	100	UVM_INFO @ 29186456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45821988180305852003317373463529728962241832409241370533612902495065828532238	100	UVM_INFO @ 141362348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7159597755333336113267231107628904487778854602279463822383254469648793010526	110	UVM_INFO @ 131214726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	45676811571723565600430090135249382772910058618357997633885696857072934844796	100	UVM_INFO @ 56427241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	98886595149329841537994464416145238911605446995701441935238300389494882022904	100	UVM_INFO @ 366489182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	30008062574888144143593980589928473375603147697723084159601979852616898345034	100	UVM_INFO @ 64679811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				10 test runs
	csrng_regwen	47876841528753106816624403105051341103972802563159154660571385819931251733818	99	UVM_INFO @ 12621480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	56147932071370584368983836244764680950137176100818790164453607823614777089219	99	UVM_INFO @ 3555444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	75688243252955299709805746503154800645560798050258729104364821512384056935917	99	UVM_INFO @ 52205624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	114944540806875914262846575868414890174678713924765651109950900692810048802477	99	UVM_INFO @ 2873659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	11236342042068860533336728917454236056808714386246475814522541991553652344246	99	UVM_INFO @ 11760572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	1144924758277017723680911010486261320056812037854277890955415890706950273402	99	UVM_INFO @ 5702546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	70128557337347355942519045486353502227320489720617124547109484777057976977724	99	UVM_INFO @ 12151103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	80454657210798876547889583197103423611564992597013667868431117645336132976771	99	UVM_INFO @ 37978501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	73676835030347983805007687042810866411058494056549847119672452002610927070273	99	UVM_INFO @ 5442598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	15769054798426997518646851868446385406750662029112622003731354923494937436404	99	UVM_INFO @ 11579358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				5 test runs
	csrng_stress_all	109943454007497895986125287966795640729391677973745826014809605289750290768528	125	UVM_INFO @ 9997368760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	99418873695635180737265580774688887262156204632611600985181531891883698168273	289	UVM_INFO @ 10292321675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	18813124781282803212646458821450195579211927208151974913999065042126833123597	134	UVM_INFO @ 5194669047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	32729038605063256167108753207790051291329281742279728128296832410583325890805	124	UVM_INFO @ 1160533431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	41280300211245091819668966808855542451716472856597844424193961625107544012216	113	UVM_INFO @ 3924447136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				5 test runs
	csrng_stress_all_with_rand_reset	100384486250404634488115810961921161771231611302480803490463290111909548736801	None
	csrng_stress_all_with_rand_reset	33580379975618615826999786898791174447452217755107598732518757184436442081464	None
	csrng_stress_all_with_rand_reset	51652815811367042384994391034435920777255062275266757293693382243917940140608	None
	csrng_stress_all_with_rand_reset	52971551127511663177953406801540962302402436944129664192166460310948657408130	None
	csrng_stress_all_with_rand_reset	79603842661894197597856385936872128956147738492799524563431880605189719587657	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				2 test runs
	csrng_regwen	66946321736794220563984774133711478659929696939288738554379223070313298503545	99	UVM_INFO @ 1826766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	77057224180034234475080441478341110492238166368180705593201280044873353444385	99	UVM_INFO @ 3220306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				2 test runs
	csrng_stress_all_with_rand_reset	68524738910947747102961307105436988969960446621654713588985191318072456842044	209	UVM_INFO @ 3110661636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	103163952231674400322022151958032860099171462461116857182466527911702027238075	110	UVM_INFO @ 43905548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	14336214633629580686489767777985233148266091115795321196991969624635354113100	103	UVM_INFO @ 132280103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				1 test run
	csrng_cmds	88790689964101021757644711819548727554012032545416084606470233021383182239838	109	UVM_INFO @ 21431047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_err_vseq] wait timeout occurred!				1 test run
	csrng_err	101858391333031707022029634905795378320212747497099532571105732113358363069788	99	UVM_INFO @ 10000871896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---